DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
Application 18/790547 claims priority to two provisional applications under 35 U.S.C. § 119(e): 63/562,907 filed March 8, 2024, and 63/572,512 filed April 1, 2024. Neither provisional application provides adequate written-description support for the full scope of the non-provisional claims. Provisional application 63/562,907 consists solely of a single-sentence specification with no claims and no disclosure of the dual-mode register circuits (transfer in a first operation mode and latch in a second operation mode), the compare circuit, the sense-amplifier coupling, the multiplexer selection logic, or the specific sequencing of repair read prior to power down. Provisional application 63/572,512 contains a single claim with partial overlap of independent Claim 1, but is silent on the second (latching) mode, the NAND gate control logic, and the multiplexer replacement of data bits with repair values. Because neither provisional discloses the complete subject matter of independent claims 1, 12, or 18, nor the relevant features of the dependent claims, the provisionals cannot support an earlier effective filing date for the claimed invention. Accordingly, the effective filing date for all claims remains the non-provisional filing date of July 31, 2024.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on October 23, 2025 has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01.
Regarding Claim 1 and the similar limitations of Claims 12 and 18: Independent claims recite limitations of a “First operation mode” and a “Second operation mode” but never explicitly define the first and/or second operation modes in the claims or the specification. Examples of various operation modes are given; for instance, ¶17 includes disclosures of a power down mode, a repair read mode, a normal read mode, and multiple references to a generic ‘operation mode.’ All descriptions are generic and indefinite, however, and fail to clearly define the metes and bounds of the claims. In the interest of compact prosecution, the first mode will be read as a repair read (transfer) mode and the second mode will be read as a latching mode.
Regarding Claims 2-11, 13-17, and 19-20: Rejected as depending from a rejected independent claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12-16 and 18-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 7,152,187 B2 to Tam Minh Tran, et al. (hereafter Tran).
Regarding Independent Claim 12, Tran discloses a memory circuit, comprising:
a memory array (A memory array: Tran, Figure 2) comprising
a plurality of first memory cells (A set of first memory cells SRAM 1 10: Tran, Figure 2) and
a plurality of second memory cells (A set of second memory cells E-Fuse Farm 26: Tran, Figure 2),
each of the plurality of first memory cells configured to store a data bit (Disclosing an SRAM, implying data memory storage: Tran, col.3:64) and
each of the plurality of second memory cells configured to store a repair bit (The E-Fuse Farm storing repair data: Tran, col.1:14-18); and
a plurality of register circuits (A set of repair registers: Tran, col.3:34); and
wherein each of the plurality of register circuits is configured to:
receive the repair bit from a corresponding one of the plurality of second memory cells (Scanning repair data from the E-Fuse Farm 26 to the repair registers: Tran, col.3:52-55; Note, presented as ‘rescanning’, implying the existence of an initial scan); and
latch the received repair bit in the register circuit when the memory circuit is configured in a power down mode (Latching the repair bit in the register circuit when the memory circuit enters a power down mode: Tran, col.4:22-24) through at least a first control signal (As managed by a SAVE signal: Tran, col.4:24-29).
Regarding Claim 13, Tran discloses the memory circuit of claim 12, wherein
each of the plurality of register circuits is configured to transfer the received repair bit to a later stage circuit (Restoring the repair data to a later stage circuit: Tran, col.4:29-31)
when the memory circuit is configured in a repair read mode through at least the first control signal and a second control signal (Restoring the repair data in response to control signals: Tran, col.4:29-31).
Regarding Claim 14, Tran discloses the memory circuit of claim 13, wherein
the repair read mode is configured to occur prior to the power down mode (Disclosing the repair data being isolated in the retention circuit prior to entering power down mode: Tran, col.4:27-29).
Regarding Claim 15, Tran discloses the memory circuit of claim 13, wherein
the first control signal is provided at a first logic state when the memory circuit is configured in the power down mode (Functional NAND gate 52, disclosing signals SR and SRB, wherein the first signal may indicate store or transfer modes, depending on bit: Tran, Figure 4 and col.4:19-29), and
the first control signal and the second control signal are provided at a second logic state and the first logic state, respectively, when the memory circuit is configured in the repair read mode (Functional NAND gate 52, disclosing signals SR and SRB, wherein the first signal may indicate store or transfer modes, depending on bit: Tran, Figure 4 and col.4:19-29).
Regarding Claim 16 and the substantially similar limitations of Claim 20, Tran discloses the memory circuit of claim 12, wherein each of the plurality of register circuits comprises at least:
a NAND gate (Disclosing at least one NAND gate: Tran, Figure 4);
a first transmission gate (Disclosing a first transmission gate: Tran, Figure 4);
a second transmission gate (Disclosing a second transmission gate: Tran, Figure 4);
a first inverter (Disclosing a first inverter: Tran, Figure 4); and
a second inverter (Disclosing a second inverter: Tran, Figure 4).
Regarding Independent Claim 18, Tran discloses a method for operating a memory circuit, comprising:
entering a memory circuit into a repair read mode (Disclosing reading repair data into a retention latch in a repair read mode: Tran, col.3:52-54)
based on a first combination of logic states of a first control signal and a second control signal (The repair data read based on a combination of signals: Tran, col.4:24-29),
after powering up the memory circuit (Repair data read taking place before entering into a power down mode, thereby implying it takes place during a power up mode: Tran, col.4:24-29),
wherein the repair read mode comprises transferring a repair bit to a register circuit (Transferring repair data from an eFuse farm to repair registers: Tran, col.3:52-54); and
entering the memory circuit into a power down mode (Entering into a power down mode: Tran, col.3:50-51)
based on a second combination of the logic states of the first control signal and the second control signal (The repair data read based on a combination of signals: Tran, col.4:24-29),
following the repair read mode (Data stored in the retention circuit following a repair read mode: Tran, col.4:27-29),
wherein the power down mode comprises latching the repair bit in the register circuit (The repair data being maintained in the retention circuit during a power down mode: Tran, col.4:22-24).
Regarding Claim 19, Tran discloses the method of claim 18, further comprising
entering the memory circuit into a normal read mode right after the power down mode (Restoring repair data from the retention latch after exiting retention or off mode: Tran, col.4:29-31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 3-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7,152,187 B2 to Tam Minh Tran, et al. (hereafter Tran) in view of US 2009/0251978 A1 to Kevin W. Gorman, et al. (hereafter Gorman).
Regarding Independent Claim 1, Tran discloses a memory circuit, comprising:
a memory array (A memory array: Tran, Figure 2) comprising
a plurality of first memory cells (A set of first memory cells SRAM 1 10: Tran, Figure 2) and
a plurality of second memory cells (A set of second memory cells E-Fuse Farm 26: Tran, Figure 2),
each of the plurality of first memory cells configured to store a data bit (Disclosing an SRAM, implying data memory storage: Tran, col.3:64) and
each of the plurality of second memory cells configured to store a repair bit (The E-Fuse Farm storing repair data: Tran, col.1:14-18);
a plurality of register circuits (A set of repair registers: Tran, col.3:34); and
wherein each of the plurality of register circuits is configured to:
receive the repair bit from a corresponding one of the plurality of second memory cells (Scanning repair data from the E-Fuse Farm 26 to the repair registers: Tran, col.3:52-55; Note, presented as ‘rescanning’, implying the existence of an initial scan); and
latch the received repair bit in the register circuit when the memory circuit is configured in a second operation mode (Latching repair data in the register during a second operation mode: Tran, col.4:22-24).
Tran does not disclose a compare circuit nor transferring the received repair bit to the compare circuit when the memory is configured in a first operation mode. Gorman, however, discloses a memory device including:
a compare circuit coupled to the plurality of register circuits (A comparator coupled to the registers: Gorman, ¶[0031]);
the plurality of register circuits configured to:
transfer the received repair bit to the compare circuit when the memory circuit is configured in a first operation mode (Loading repair bit data to a repair ring in a first operation mode: Gorman, ¶[0038]);
Gorman teaches the use of a comparator combined with an address register allows use of a single controller for multiple repair data (Gorman, ¶[0038]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the serial comparator of Gorman with the persistent repair bit register of Tran, with a reasonable expectation of success. Both inventions are well known techniques of efficient repair bit analysis and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 3, Tran discloses the memory circuit of claim 1, wherein each of the plurality of register circuits comprises at least:
a NAND gate (Disclosing at least one NAND gate: Tran, Figure 4);
a first transmission gate (Disclosing a first transmission gate: Tran, Figure 4);
a second transmission gate (Disclosing a second transmission gate: Tran, Figure 4);
a first inverter (Disclosing a first inverter: Tran, Figure 4); and
a second inverter (Disclosing a second inverter: Tran, Figure 4).
Regarding Claim 4, Tran discloses the memory circuit of claim 3, wherein
the NAND gate is configured to receive a first signal and a second signal (At a minimum, a NAND gate receives a first and second signal by definition), and
wherein the first signal is provided at a first logic state in the second operation mode, and at a second logic state in the first operation mode (Functional NAND gate 52, disclosing signals SR and SRB, wherein the first signal may indicate store or transfer modes, depending on bit: Tran, Figure 4 and col.4:19-29).
Regarding Claim 5, Tran discloses the memory circuit of claim 4, wherein
the first signal (The RESTORE signal: Tran, Figure 4),
when provided at the first logic state, corresponds to the second operation mode, regardless of a logic state of the second signal (RESTORE corresponding to the operation mode regardless of the state of CLRZ: Tran, Figure 4).
Regarding Claim 6, Tran discloses the memory circuit of claim 4, wherein
the second signal,
when provided at the first logic state, corresponds to the second operation mode, with the first signal provided at the second logic state (Disclosing signals SR and SRB, wherein the second signal may indicate store or transfer modes, when the first signal is in a second logic state: Tran, Figure 4 and col.4:19-29), and
wherein the second signal,
when provided at the second logic state, corresponds to the first operation mode, with the first signal provided at the second logic state (Disclosing signals SR and SRB, wherein the second signal may indicate store or transfer modes, when the first signal is in a second logic state: Tran, Figure 4 and col.4:19-29).
Regarding Claim 7, Tran discloses the memory circuit of claim 3, wherein,
in the first operation mode,
the first transmission gate is activated to pass a currently received repair bit to the compare circuit (The signals restoring repair data from the retention latch: Tran, col.4:29-31).
Regarding Claim 8, Tran discloses the memory circuit of claim 7, wherein,
in the second operation mode, the first transmission gate is deactivated, which causes a previously received repair bit to be latched within the second transmission gate, the first inverter, and the second inverter (Signals isolating the latch circuitry during data retention or off modes: Tran, col.4:27-29).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7,152,187 B2 to Tam Minh Tran, et al. (hereafter Tran) and US 2009/0251978 A1 to Kevin W. Gorman, et al. (hereafter Gorman), further in view of US 8,356,212 B2 to Klaus J. Oberlaender (hereafter Oberlaender).
Regarding Claim 2, Tran discloses the memory circuit of claim 1, but fails to expressly disclose what data constitutes repair data. Oberlaender, however, discloses a memory circuit including repair data, wherein
a plural number of the repair bits are collectively associated with a corresponding one of the plurality of first memory cells (Disclosing repair data consisting of a copy of the data, an address, and a valid bit, necessitating plural bits associated with the single faulty memory cell: Oberlaender, col.6:17-20), and
wherein the plural number of the repair bits indicate
a location of the corresponding first memory cell in the memory array (Repair data including an address: Oberlaender, col.6:17-20),
whether the plural number of the repair bits are still capable of repairing (Repair data including a valid bit: Oberlaender, col.6:17-20; The valid bit indicating whether the fault may be repaired: Oberlaender, col.6:24-28), and
whether the corresponding first memory cell is to be repaired as logic 0 or logic 1 (Repair data including the original bit data: Oberlaender, col.6:17-20).
Oberlaender discloses this data allows the memory circuit to react to a failure using existing application software, allowing the eventual repair of the problem without losing data (Oberlaender, col.6:21-28). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, that the clear data outlined by Oberlaender might describe the repair data disclosed by Tran, with a reasonable expectation of success. Both inventions are well known in the field of repair bit analysis and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7,152,187 B2 to Tam Minh Tran, et al. (hereafter Tran) and US 2009/0251978 A1 to Kevin W. Gorman, et al. (hereafter Gorman), further in view of US 9,158,619 B2 to Darshan Kobla, et al. (hereafter Kobla).
Regarding Claim 9, Tran discloses the memory circuit of claim 1, but fails to expressly disclose the further limitations of Claim 9. Kobla, however, discloses a memory repair circuit, further comprising
a multiplexer (A multiplexer: Kobla, col.3:29) configured to:
receive the stored data bit and the repair bits from the memory array and the compare circuit, respectively (Receiving a bit from Content Addressable Memory and DRAM: Kobla, col.3:30-31);
select one or more of the repair bits as a first output signal when the memory circuit is configured in the first operation mode (The multiplexer choosing between the data from the CAM or the DRAM: Kobla, col.3:29-31).
Kobla teaches the disclosed repair methodologies may be supplier independent, do not require modification of other redundancy processes, support both static and dynamic repair protocols, and/or may allow conventional memory subsystems to circumvent memory cell failures (Kobla, col.2:49-64). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the multiplexer of Kobla with the repair data architecture of Tran, with a reasonable expectation of success. Both inventions are well known in the field of faulty memory cell repair and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 10, Kobla discloses the memory circuit of claim 9, wherein, when the memory circuit is configured in the first operation mode,
the compare circuit is configured to:
receive an address signal indicating a location of a corresponding one of the plurality of first memory cells in the memory array (Receiving an address for a memory operation: Kobla, col.3:21-22);
compare the address signal with one or more of the repair bits transferred by the respective register circuits (Comparing the address to one or more repair data: Kobla, col.3:22-23); and
provide a second output signal in response to a match between the address signal and the one or more repair bits (Providing a signal if there is a positive match between the requested address and repair data: Kobla, col.3:25-29; See also, Kobla, col.6:41-43).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7,152,187 B2 to Tam Minh Tran, et al. (hereafter Tran), US 2009/0251978 A1 to Kevin W. Gorman, et al. (hereafter Gorman), and US 9,158,619 B2 to Darshan Kobla, et al. (hereafter Kobla), further in view of US 7,821,862 B2 to Takesada Akiba, et al. (hereafter Akiba).
Regarding Claim 11, Kobla discloses the memory circuit of claim 10, but fails to disclose the further limitations of Claim 11. Akiba, however, discloses a memory circuit as in Claim 10, further comprising
a sense amplifier circuit (Sense amplifier circuit SA: Akiba, Figure 1) operatively coupled between the memory array and the plurality of register circuits (The sense amplifier SA coupled between the memory array and the register circuits: Akiba, Figure 1).
Akiba teaches the sense amplifier is capable of amplifying a small potential difference to a high and low level, similar to the original storage state (Akiba, col.5:62-66). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the sense amplifier of Akiba with the repair data architecture of Tran and Kobla, with a reasonable expectation of success. Both inventions are well known in the field of memory array repair reading and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7,152,187 B2 to Tam Minh Tran, et al. (hereafter Tran) in view of US 8,356,212 B2 to Klaus J. Oberlaender (hereafter Oberlaender).
Regarding Claim 17, Tran discloses the memory circuit of claim 12 but fails to disclose the further limitations of Claim 17. Oberlaender, however, discloses a memory circuit as in Claim 12, wherein
a plural number of the repair bits are collectively associated with a corresponding one of the plurality of first memory cells (Disclosing repair data consisting of a copy of the data, an address, and a valid bit, necessitating plural bits associated with the single faulty memory cell: Oberlaender, col.6:17-20), and
wherein the plural number of the repair bits indicate
a location of the corresponding first memory cell in the memory array (Repair data including an address: Oberlaender, col.6:17-20),
whether the plural number of the repair bits are still capable of repairing (Repair data including a valid bit: Oberlaender, col.6:17-20; The valid bit indicating whether the fault may be repaired: Oberlaender, col.6:24-28), and
whether the corresponding first memory cell is to be repaired as logic 0 or logic 1 (Repair data including the original bit data: Oberlaender, col.6:17-20).
Oberlaender discloses this data allows the memory circuit to react to a failure using existing application software, allowing the eventual repair of the problem without losing data (Oberlaender, col.6:21-28). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, that the clear data outlined by Oberlaender might describe the repair data disclosed by Tran, with a reasonable expectation of success. Both inventions are well known in the field of repair bit analysis and the combination of known inventions with predictable results is obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2015/0339202 A1 to Frederick A. Ware, et al.: Disclosing repair data fields including address and tags indicating the repair data is to replace first data on retrieve.
US 2018/0039538 A1 to Guy Freikorn, et al.: Disclosing error detection modes, including retrieving redundancy data.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824