DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 6, 7, 9 and 18-20 of U.S. Patent No. 12,136,460. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-14 are anticipated by claims 1, 2, 4, 6, 7 and 9 of the patent and claims 15-20 would have been obvious over, the reference claims 18-20 of the patent.
Regarding claim 1, claim 1 of the patent recites a memory circuit comprising:
first and second write lines coupled to first and second memory segments (claim 1, lines 2-4);
a power supply node configured to carry a power supply voltage level (claim 2, line 4);
a reference node configured to carry a reference voltage level (claim 2, line 7;
a first driving circuit (claim 1, line 5, a first write line circuit and claim 2) comprising:
a first PMOS transistor coupled in series with a first inverter between the power supply node and the reference node, wherein the first inverter comprises an input coupled to a first input node of the first driving circuit and an output coupled to the first write line (claim 2); and
a second inverter coupled between a gate of the first PMOS transistor and a second input node of the first driving circuit; and
a second driving circuit (claim 1, line 7, a second write line and claim 2) comprising:
a second PMOS transistor coupled in series with a third inverter between the power supply node and the reference node, wherein the third inverter comprises an input coupled to a first input node of the second driving circuit and an output coupled to the second write line; and
a fourth inverter coupled between a gate of the second PMOS transistor and a second input node of the second driving circuit,
wherein:
each of the first input node of the first driving circuit and the second input node of the second driving circuit is configured to receive a first data signal (claim 2, lines 11-14), and
each of the second input node of the first driving circuit and the first input node of the second driving circuit is configured to receive a second data signal (claim 2, lines 15-18).
Regarding claim 2, claim 1 of the patent recites the memory circuit of claim 1, wherein the memory circuit is configured to propagate the first and second data signals as a complementary pair during write operations and each having a low logical state during masked write operations (claim 1, lines 11-18).
Regarding claim 3, claim 1 of the patent recites the memory circuit of claim 2, wherein the memory circuit is configured to propagate the first and second data signals each having the low logical state between the write and masked write operations.
Regarding claim 4, claim 4 of the patent recites the memory circuit of claim 3, wherein the memory circuit is further configured to couple each of the first and second write lines to the power supply node between the write and masked write operations.
Regarding claim 5, claim 2 of the patent recites the memory circuit of claim 1, wherein
the first inverter comprises a third PMOS transistor coupled in series with a first NMOS transistor between the first PMOS transistor and the reference node,
a gate of each of the third PMOS transistor and the first NMOS transistor is coupled to the first input node of the first driving circuit,
a drain of each of the third PMOS transistor and the first NMOS transistor is coupled to the first write line,
the third inverter comprises a fourth PMOS transistor coupled in series with a second NMOS transistor between the second PMOS transistor and the reference node,
a gate of each of the fourth PMOS transistor and the second NMOS transistor is coupled to the first input node of the second driving circuit, and
a drain of each of the fourth PMOS transistor and the second NMOS transistor is coupled to the second write line.
Regarding claim 6, claim 6 of the patent recites the memory circuit of claim 1, wherein
each of the first and second memory segments comprises a selection circuit coupled between each of the first and second write lines and a plurality of columns comprising bit line pairs coupled to memory cells.
Regarding claim 7, claim 7 of the patent recites the memory circuit of claim 6, wherein the memory cells of each plurality of columns of each of the first and second memory segments comprise static random-access memory (SRAM) cells.
Regarding claim 8, claims 1, 2 and 4 of the patent recite a memory circuit comprising:
first and second write lines coupled to first and second memory segments;
a power supply node configured to carry a power supply voltage level;
a reference node configured to carry a reference voltage level;
a first driving circuit comprising:
a first PMOS transistor coupled in series with a first inverter between the power supply node and the reference node, wherein the first inverter comprises an input coupled to a first input node of the first driving circuit and an output coupled to the first write line; and
a second inverter coupled between a gate of the first PMOS transistor and a second input node of the first driving circuit;
a first pre-charge circuit coupled between the power supply node and the output of the first inverter (claim 4);
a second driving circuit comprising:
a second PMOS transistor coupled in series with a third inverter between the power supply node and the reference node, wherein the third inverter comprises an input coupled to a first input node of the second driving circuit and an output coupled to the second write line; and
a fourth inverter coupled between a gate of the second PMOS transistor and a second input node of the second driving circuit; and
a second pre-charge circuit coupled between the power supply node and the output of the third inverter (claim 4);
wherein:
each of the first input node of the first driving circuit and the second input node of the second driving circuit is configured to receive a first data signal, and
each of the second input node of the first driving circuit and the first input node of the second driving circuit is configured to receive a second data signal (claim 2).
Regarding claim 9, claim 4 of the patent recites the memory circuit of claim 8, wherein
the first pre-charge circuit comprises third and fourth PMOS transistors coupled in series between the power supply node and the output of the first inverter,
the second pre-charge circuit comprises fifth and sixth PMOS transistors coupled in series between the power supply node and the output of the third inverter,
a gate of each of the third and fifth PMOS transistors is configured to receive a first enable signal, and
a gate of each of the fourth and sixth PMOS transistors is configured to receive a second enable signal.
Regarding claim 10, claim 6 of the patent recites the memory circuit of claim 9, wherein
the first memory segment comprises a first column of memory cells coupled to a first bit line pair and a first bit line pre-charger configured to receive the first enable signal, and
the second memory segment comprises a second column of memory cells coupled to a second bit line pair and a second bit line pre-charger configured to receive the second enable signal.
Regarding claim 11, claims 1 and 4 of the patent recite the memory circuit of claim 10, wherein the memory circuit is configured to:
during write operations, propagate the first and second data signals as a complementary pair (claim 1, lines 12-14)),
during masked write operations, propagate the first and second data signals each having a low logical state (claim 1, lines 16-18),
during each of the write and masked write operations corresponding to the first memory segment, propagate the first enable signal having the high logical state and the second enable signal having the low logical state, and
during each of the write and masked write operations corresponding to the second memory segment, propagate the second enable signal having the high logical state and the first enable signal having the low logical state (claim 4).
Regarding claim 12, claims 1 and 5 of the patent recite the memory circuit of claim 11, wherein
the memory circuit is configured to, between each of the write and masked write operations, propagate the first and second data signals and the first and second enable signals each having the low logical state.
Regarding claim 13, claim 7 of the patent recites the memory circuit of claim 11, wherein
the first memory segment comprises a first selection circuit configured to couple the first bit line pair to the first and second write lines during each of the write and masked write operations corresponding to the first memory segment, and
the second memory segment comprises a second selection circuit configured to couple the second bit line pair to the first and second write lines during each of the write and masked write operations corresponding to the second memory segment.
Regarding claim 14, claim 9 of the patent recites the memory circuit of claim 10, wherein
each of the first and second columns of memory cells comprises static random-access memory (SRAM) cells.
Regarding claim 15, claim 18 of the patent recites a method of operating a memory circuit, the method comprising:
propagating a first data signal to each of a first input node of a first driving circuit of the memory circuit and a second input node of a second driving circuit of the memory circuit; and
propagating a second data signal to each of a second input node of the first driving circuit and a first input node of the second driving circuit, wherein
the memory circuit comprises:
first and second write lines coupled to first and second memory segments;
a power supply node configured to carry a power supply voltage level; and
a reference node configured to carry a reference voltage level, the first driving circuit comprises:
a first PMOS transistor coupled in series with a first inverter between the power supply node and the reference node, wherein the first inverter comprises an input coupled to the first input node of the first driving circuit and an output coupled to the first write line; and
a second inverter coupled between a gate of the first PMOS transistor and the second input node of the first driving circuit, and the second driving circuit comprises:
a second PMOS transistor coupled in series with a third inverter between the power supply node and the reference node, wherein the third inverter comprises an input coupled to the first input node of the second driving circuit and an output coupled to the second write line; and
a fourth inverter coupled between a gate of the second PMOS transistor and the second input node of the second driving circuit.
Regarding claim 16, claim 18 of the patent recites the method of claim 15, wherein
the propagating the first and second data signals comprises propagating the first and second data signals as a complementary pair during write operations and propagating each of the first and second data signals having a low logical state during masked write operations.
Regarding claim 17, claim 18 of the patent recites the method of claim 16, wherein
the propagating the first and second data signals further comprises propagating each of the first and second data signals having the low logical state between the write and masked write operations.
Regarding claim 18, claims 18-20 of the patent recite the method of claim 17, wherein
the memory circuit further comprises:
third and fourth PMOS transistors coupled in series between the power supply node and the output of the first inverter; and
fifth and sixth PMOS transistors coupled in series between the power supply node and the output of the third inverter, and
the method further comprises propagating a first enable signal to a gate of each of the first and third PMOS transistors and a second enable signal to a gate of each of the second and fourth PMOS transistors, wherein
the first enable signal has the high logical state during the write and masked write operations corresponding to the first memory segment,
the second enable signal has the high logical state during the write and masked write operations corresponding to the second memory segment, and each of the first and second enable signals has the low logical state between the write and masked write operations.
Regarding claim 19, the method of claim 18, wherein
the propagating the first enable signal comprises propagating the first enable signal to a bit line pre-charger of the first memory segment, and
the propagating the second enable signal comprises propagating the second enable signal to a bit line pre-charger of the second memory segment.
Regarding claim 20, claims 18-20 recite the method of claim 18, further comprising:
coupling a bit line pair of the first memory segment to the first and second write lines during the write and masked write operations corresponding to the first memory segment; and
coupling a bit line pair of the second memory segment to the first and second write lines during the write and masked write operations corresponding to the second memory segment.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, 10 and 15-20 of U.S. Patent No. 11,798,632. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1.and 5 are anticipated by claims 7 and 10 of the patent and claims 1, 2-4, 6 and 8-20
Regarding claim 1, claim 7 of the patent recites a memory circuit comprising:
first and second write lines coupled to first and second memory segments (claim 7, lines 2-3);
a power supply node configured to carry a power supply voltage level (claim 7, lines 7-8);
a reference node configured to carry a reference voltage level (claim 7, lines 9-10);
a first driving circuit (claim 7, a first write line circuit) comprising:
a first PMOS transistor coupled in series with a first inverter (a second PMOS and an NMOS in claim 7) between the power supply node and the reference node, wherein the first inverter comprises an input coupled to a first input node of the first driving circuit and an output coupled to the first write line (claim 7); and
a second inverter (claim 10) coupled between a gate of the first PMOS transistor and a second input node of the first driving circuit; and
a second driving circuit (claim 7, a second write line circuit) comprising:
a second PMOS transistor coupled in series with a third inverter (claim 7, a second PMOS and an NMOS in claim 7 for each of the first and second write line circuits) between the power supply node and the reference node, wherein the third inverter comprises an input coupled to a first input node of the second driving circuit and an output coupled to the second write line; and
a fourth inverter (claim 10) coupled between a gate of the second PMOS transistor and a second input node of the second driving circuit,
wherein:
each of the first input node of the first driving circuit and the second input node of the second driving circuit is configured to receive a first data signal (claims 9 and 10), and
each of the second input node of the first driving circuit and the first input node of the second driving circuit is configured to receive a second data signal (claims 9 and 10).
Regarding claim 5, claim 7 of the patent recites the memory circuit of claim 1, wherein
the first inverter (claim 7) comprises a third PMOS transistor coupled in series with a first NMOS transistor between the first PMOS transistor and the reference node,
a gate of each of the third PMOS transistor and the first NMOS transistor is coupled to the first input node of the first driving circuit,
a drain of each of the third PMOS transistor and the first NMOS transistor is coupled to the first write line,
the third inverter (claim 7) comprises a fourth PMOS transistor coupled in series with a second NMOS transistor between the second PMOS transistor and the reference node,
a gate of each of the fourth PMOS transistor and the second NMOS transistor is coupled to the first input node of the second driving circuit, and
a drain of each of the fourth PMOS transistor and the second NMOS transistor is coupled to the second write line.
Regarding claims 6, 8-10, 13 and 14, it would have been obvious to one having ordinary skill in the art to recognize that a write line circuit in claim 1 is one of the first and second write line circuits in claim 7.
Regarding claims 6 and 10, claims 1 and claim 7 of the patent recite the memory circuit of claim 1, wherein
each of the first and second memory segments comprises a selection circuit coupled between each of the first and second write lines and a plurality of columns comprising bit line pairs coupled to memory cells.
Claims 4 and 7 of the patent recite the first and second pre-charge circuits as recited in claims 8 and 9.
Regarding claim 7, claims 9 and 1 of the patent recites the memory circuit of claim 6, wherein the memory cells of each plurality of columns of each of the first and second memory segments comprise static random-access memory (SRAM) cells.
Regarding claims 2-4, 11 and 12, it would have been obvious to one having ordinary skill in the art to recognize that the memory circuit of claim 2-4, 11 and 12 of the instant application and the memory circuit of claims 1, 7 and 10 of the patent are identical in structure; therefore, the differences between two sets of claims are only functional limitations.
Regarding claim 13, claim 1 and 7 of the patent recites the memory circuit of claim 11, wherein
the first memory segment comprises a first selection circuit configured to couple the first bit line pair to the first and second write lines during each of the write and masked write operations corresponding to the first memory segment, and
the second memory segment comprises a second selection circuit configured to couple the second bit line pair to the first and second write lines during each of the write and masked write operations corresponding to the second memory segment.
Regarding claim 14, claims 1 and 9 of the patent recites the memory circuit of claim 10, wherein
each of the first and second columns of memory cells comprises static random-access memory (SRAM) cells.
Regarding claims 15-20, it would have been obvious to one having ordinary skill in the art to use the memory circuit of claims 1, 7 and 10 and the method of claims 15-20 of the patent to perform the method of claims 15-20 of the instant application.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,011,238. Although the claims at issue are not identical, they are not patentably distinct from each other because it would have been obvious to one having ordinary skill in the art to recognize that the write line circuit of claims 1-6 of the patent is one of first and second write line circuits of a memory macro in claim 9 of the patent and the switches in claims 1-16 of the patent correspond to the PMOS ad NMOS transistors of claims 1-4 and the write line circuit of claim 1-16 and the method of claims 17-20 of the patent are used to perform the method of claims 15-20.
Conclusion
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/HUAN HOANG/ Primary Examiner, Art Unit 2154