DETAILED ACTION
The present application, filed on (7/31/2024), is being examined under the first inventor to file provisions of the AIA . Claims (1-20) are pending and being examined.
Claim Interpretation
The term “pattern transfer processing chamber” is interpreted as a process chamber capable of plasma processing a substrate. The specification discloses pattern transfer as being implemented by processing a substrate including a pattern previously disposed on it.
The term “embedded baking chamber” is disclosed in the specification as a box 106 attached to and being accessible from transfer chamber 103. Claims 6 and 9-15 require baking chamber as being embedded in the load-lock being part of the claimed second region. It is interpreted as a means for heating substrates held in the load-lock. It is noted that the disclosure of Fig 1A does not appear to follow the text of the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8 and 16-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kamata et al (US 20160013084).
Kamata et al disclose a semiconductor processing tool (Fig 1 and abstract) comprising:
a pattern transfer processing chamber (Abstract discloses a chamber).
a loading area external to the pattern transfer processing chamber and configured to transfer a wafer to or from the pattern transfer processing chamber, wherein the loading area comprises:
a first region including a load port (EFEM Fig 1).
a second region between the first region and the pattern transfer processing chamber, the second region including a load-lock (Fig 3, 31); and
an embedded baking chamber configured to heat a patterned photoresist on the wafer is disclosed (Fig 2A 2B, 4). Baking apparatus is installed in EFEM (Para 26, 39-41) which is part of the first region and is in atmosphere and includes atmospheric robot (Fig 3, 35 and Para 42).
Regarding claim 2, 3, 17 and 18 Kamata et al disclose that the process chamber could be anything plasma, thermal or radical processing (Para 27) which would include etching and ion implantation processing chamber.
Regarding claim 4, 5 19 and 20 embedded chamber section is included in the first region as being attached to EFEM (Para 26, 39-41) which is part of the first region and is in atmosphere and includes atmospheric robot (Fig 3, 35 and Para 42).
Regarding claim 8, claimed pressure is in a vacuum range and is well known and established in prior art. This, however, is a functional limitation and discussed later Ken Okutani discloses chamber pressure up to 10-6 torr.
Claim 16 is rejected with claim 1 as including all the limitations of that claim.
Claims 1-2, 6-12 and 14-15 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Bramhall et al (US 4923584).
Bramhall et al disclose a semiconductor processing tool (Fig 1) comprising:
a pattern transfer processing chamber (16, 17, 18 and 19).
a loading area external to the pattern transfer processing chamber and configured to transfer a wafer to or from the pattern transfer processing chamber, wherein the loading area comprises:
a first region including a load port (12).
a second region between the first region and the pattern transfer processing chamber, the second region including a load-lock (22); and a heating unit comprising a halogen lamp in the load lock (45) as being an embedded baking chamber.
Regarding claim 2 Bramhall et al disclose that the process chamber could be anything plasma, thermal or radical processing (Para 27) which would include etching and ion implantation processing chamber.
Regarding claim 6 and 7, as noted above is disclosed a heating unit comprising a halogen lamp in the load lock (45) as being an embedded baking chamber.
Regarding claim 8 and 15, the claimed pressure is in a vacuum range and is well known and established in prior art. This however is a functional limitation and discussed later Ken Okutani discloses chamber pressure up to 10-6 torr.
Claim 9 is disclosed as above since it includes processing chamber, load-lock and embedded baking chamber.
Regarding claim 10 atmospheric robot (37) is disclosed.
Regarding claim 11 bake chamber heating is by halogen lamp 45.
Regarding claim 12 etching process module is disclosed (Col 6 lines 46-59).
Regarding claim 14 plurality of load locks (22) and load ports are disclosed (28).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 and 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kamata et al (US 20160013084) in view of Ken Okutani (US 5135608).
Regarding claims 6-7 and 9-20 Kamata et al disclose all the limitations except bake chamber included in the load-lock.
Ken Okutani discloses a cluster tool including load lock and process chamber and include heating means (14) in a load lock (621 and Col 11 lines 31-53).
It would have been obvious for one of the ordinary skill in the art before the effective filing date of this application to relocate baking chamber in load lock to prevent being exposed to atmosphere before chamber processing.
Claims 1-5, 7-8, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Caveney et al (US 20120128450) in view of Yoshitake Ito (US 20080011713).
Caveney et al disclose a semiconductor processing tool (Fig 1, 100) comprising:
a pattern transfer processing chamber (Fig 1, 125) included in a process module.
a loading area external to the pattern transfer processing chamber and configured to transfer a wafer to or from the pattern transfer processing chamber (Robot 120),
wherein the loading area comprises:
a first region including a load port (115).
a second region between the first region and the pattern transfer processing chamber, the second region including a load-lock (135, 140).
Caveney et al suggest the possibility of including another station or section embedded in the atmospheric transfer chamber at the location of (162) but do not particularly disclose that this is an embedded baking chamber.
Yoshitake Ito discloses a photoresist processing apparatus for the processing of substrate for pattern transfer and discloses an interface unit including a transfer unit section 6 and an embedded baking section which is configured to heat a substrate received from an exposure apparatus (3)
Regarding claims 2, 3, 17 and 18 Caveney et al disclose chamber 125 to be etching, baking or implantation chamber.
Regarding claim 4, 5 19 and 20 embedded chamber section is included in the first region defined by 162 in Caveney et al and FH in Yoshitake Ito. Also, robot 120 is disposed in atmosphere and accessible both to place holder 162 modified by Yoshitake Ito.
Regarding claim 7 heating mechanism is a hot plate (para 90 and Fig 7). Heating with hot plate contact or halogen lamp were well known in the prior art before the effective filing date of this application.
Regarding claim 8 claimed pressure is in a vacuum range. This however is a functional limitation. As discussed before, Ken Okutani discloses chamber pressure up to 10-6 torr.
Claims 6 and 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Caveney et al (US 20120128450) in view of Yoshitake Ito (US 20080011713) and Wang et al (US 20020190051).
Caveney et al in view of Yoshitake Ito disclose all the limitations of these claims except bake chamber included in the load-lock.
Wang et al discloses a cluster tool including load lock and process chamber and include baking means in a load lock (Para 34).
It would have been obvious for one of ordinary skill in the art before the effective filing date of this application to relocate baking chamber in load lock to prevent being exposed to atmosphere before chamber processing.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kuo (US 6468918) discloses baking means in load lock (Col 1 line 56- Col 2 line 2)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAM N KACKAR whose telephone number is (571)272-1436. The examiner can normally be reached 09:00 AM-05:00 PM.
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RAM N. KACKAR
Primary Examiner
Art Unit 1716
/RAM N KACKAR/ Primary Examiner, Art Unit 1716
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