Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Objections
Claim 3 is objected to because of the following informalities: The claim should end in a period. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6 and 7 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yoon et al. (US Pub. No. 2016/0284680 A1; see Translation of KR App 20150043087 filed 03/27/2015), hereafter referred to as Yoon.
As to claim 1, Yoon discloses a first semiconductor device (fig 12; [0044]), comprising:
a first fin separated by a first recess;
a second fin separated by a second recess;
a third fin separated by a third recess;
a first continuous gate disposed along a first side of the first recess, a second side of the second recess, and across the third recess; and
a second continuous gate arranged to intersect the first fin, and disposed across the second recess and the third recess,
wherein the first continuous gate is located between the first side and the second side (see annotated figure 12 below).
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As to claim 2, Yoon discloses the semiconductor device of claim 1 (Paragraphs above),
a plurality of continuous gates (fig 12, GS),
wherein the first fin comprises a first portion and a second portion (two portions of first fin AP),
two of the plurality of continuous gates cover a side of the first portion and a side of the second portion respectively (GS covering sides of first and second portion of the first AP), and
the two of the plurality of continuous gates located at two sides of the first recess, respectively (GS at sides of the first recess as shown in annotated fig 12 above).
As to claim 3, Yoon discloses the semiconductor device of claim 2 (Paragraphs above),
wherein another two of the plurality of continuous gates are disposed across the first portion and the second portion, respectively (fig 12, gates GS(GS2) on the first and second portions of AP).
As to claim 4, Yoon discloses the semiconductor device of claim 2 (Paragraphs above),
wherein a length of the first portion is longer than a length of the second portion (fig 12, the first portion of AP is considered to be from leftmost edge to the recess while the second portion is considered to be from the recess to the opposite side of GS2 which is a shorter length than the first portion).
As to claim 6, Yoon discloses the semiconductor device of claim 1 (Paragraphs above),
a fourth fin separated by a fourth recess (see annotated fig 12 above),
wherein the first fin is located between the fourth fin and the second fin (see annotated fig 12 above), and
the first continuous gate is disposed further across the fourth recess (see annotated fig 12 above).
As to claim 7, Yoon discloses the semiconductor device of claim 1 (Paragraphs above),
wherein the first continuous gate elongates along a first direction (D2),
along the first direction (D2), the first side and a third side of the second recess are not aligned to each other, and a fourth side of the first recess and the second side are not aligned to each other (see alignments of the sides of first and second recesses).
Claim(s) 1, 7-9, 14-15, 17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shimbo (US Pub. No. 2016/0190138 A1).
As to claim 1, Shimbo discloses a first semiconductor device (fig 1, [0049]), comprising:
a first fin (fig 1, 31a) separated by a first recess (see annotated fig 1 below);
a second fin (31b) separated by a second recess (see annotated fig 1 below);
a third fin (32a) separated by a third recess (see annotated fig 1 below);
a first continuous gate disposed along a first side of the first recess, a second side of the second recess, and across the third recess (see annotated fig 1 below); and
a second continuous gate arranged to intersect the first fin, and disposed across the second recess and the third recess (see annotated fig 1 below),
wherein the first continuous gate is located between the first side and the second side (see annotated fig 1 below).
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As to claim 7, Shimbo discloses the semiconductor device of claim 1 (Paragraphs above),
wherein the first continuous gate elongates along a first direction (Y-direction),
along the first direction (Y-direction), the first side and a third side of the second recess are not aligned to each other (see annotated fig 1), and a fourth side of the first recess and the second side are not aligned to each other (see annotated fig 1).
As to claim 8, Shimbo discloses the semiconductor device of claim 7 (Paragraphs above),
wherein along a second direction (X-direction) perpendicular to the first direction (Y-direction), a distance between the first side and the second side of the first recess is longer than a distance between the first side and the second side of the third recess (see annotated fig 1 above).
As to claim 9, Shimbo discloses a semiconductor device (fig 1, [0049]), comprising:
a first fin (31b) separated by a first recess (see annotated fig 1 below);
a second fin (31c) separated by a second recess (see fig below);
a third fin (32a) separated by a third recess (see fig below);
a first continuous gate disposed across the first recess, the second recess, and the third recess (see fig below);
a second continuous gate disposed across the first recess, the third recess, and disposed along a first side of the second recess (see fig below); and
a third continuous gate arranged across the first fin, the second fin, and the third fin (see fig below),
wherein the second continuous gate is located between the first continuous gate and the third continuous gate (see fig below), and
wherein a distance between the first side and the first continuous gate is approximately equal to a distance between the first side and the third continuous gate (see annotated fig 1 below that shows that the distance is approximately equal to three gate line pitches for each of the first side to the 3rd gate as well as the first side to the 1st gate).
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As to claim 14, Shimbo discloses the semiconductor device of claim 9 (paragraphs above),
a fourth fin (fig 1, 32b) separated by a fourth recess (recess aligned with 1st recess),
a plurality of continuous gates (fig 1 gates G) disposed across the fourth fin (32b),
wherein one of the plurality of continuous gate is disposed across each of the first recess, the second recess, the third recess, and the fourth recess (gate across middle of recess region shown in annotated fig 1 above).
As to claim 15, Shimbo discloses the semiconductor device of claim 14 (paragraphs above),
wherein two of the plurality of continuous gates is disposed across each of the second recess, the fourth recess, the first fin, and the third fin (see two of the continuous gates G in annotated fig 1 above).
As to claim 17, Shimbo discloses a method (fig 1, [0018]), comprising:
forming a first fin (fig 1, 31b) separated by a first recess (see annotated fig 1 below);
forming a second fin (32c) separated by a second recess (see annotated fig 1 below);
forming a plurality of continuous gates (see annotated fig 1 below) comprising:
forming a first number of the plurality of continuous gates disposed across the first recess and the second recess (see annotated fig 1 below); and
forming a second number of the plurality of continuous gates disposed across the first recess and the second fin (see annotated fig 1 below),
wherein the second number is larger than the first number (see in annotated fig 1 below).
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As to claim 19, Shimbo discloses the method of claim 17 (paragraphs above),
forming a third fin (31c) separated by a third recess (recess aligned with 1st recess); and
forming a fourth fin (32a) separated by a fourth recess (recess aligned with 1st recess),
wherein one of the plurality of continuous gates is disposed across each of the first recess, the second recess, the third recess, and the fourth recess (see annotated fig 1 above).
As to claim 20, Shimbo discloses the method of claim 19 (paragraphs above),
wherein another one of the plurality of continuous gates is disposed across the fourth recess, and disposed along a first side of the third recess (see annotated fig 1 below).
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Allowable Subject Matter
Claims 5, 10-13, 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest a fourth continuous gate disposed across each of the fourth recess, the first recess, the second fin, and the third fin, as recited in claim 5; a plurality of continuous fin, wherein a first number of the plurality of continuous gates are disposed across the first recess, a second number of the plurality of continuous gates are disposed across the second recess, and the first number is smaller than the second number, as recited in claim 10; wherein the first continuous gate elongates along a direction, two sides of the first recess are aligned with two sides of the third recess along the direction, and the two sides of the first recess are not aligned with two sides of the second recess along the direction, as recited in claim 13; along the direction, a distance between the first side of the second recess and a second side of the second recess is longer than a distance between a first side of the first recess and a second side of the first recess, as recited in claim 16; or forming a first continuous gate disposed along a first side of the first recess, and across the second recess; forming a second continuous gate disposed across each of the first recess and the second recess; and forming a third continuous gate disposed across the first fin, the second fin, and the third fin, wherein the first continuous gate is located between the second continuous gate and the third continuous gates, as recited in claim 18. Additionally, claims 11 and 12 are objected to as allowable because they are dependent from claim 10.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2012/0126326 A1 shows the continuous gates crossing fins and recesses therein.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 10/13/2026
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