DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 31, 2024, March 5, 2025 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the exposed end surface" in line 10. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the end surface”
Claim 2 recites the limitation "the sidewall" in line 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the first sidewall”
Claim 3 recites the limitation "the sidewall" in line 4. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the first sidewall”
Note: Claims 2-5 inherit the deficiencies of claim 1.
Claim 13 recites the limitation "the transistor" in line 1. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the first transistor”
Note: Claims 14-15 inherit the deficiencies of claim 13.
Claim 16, lines: 13-14 recite the limitation “electrically connecting the first transistor to a first interconnect structure on the first side of the substrate.” It is unclear what is electrically connecting the first transistor to a first interconnect structure. For purposes of examination this will be interpreted as “electrically connecting the first transistor to a first interconnect structure on the first side of the substrate through the SIS.” Note: Claims 17-20 inherit the deficiencies of claim 16.
Allowable Subject Matter
Claims 1-5, 16-20 would be allowed if rewritten to overcome the 112 rejection above
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Greene (US 2017/0062325), Purushothaman (US 2015/0054149), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 1 (from which claims 2-5 depend), a self-aligned interconnect structure (SIS) extending through an entirety of the substrate in a thickness direction, wherein the spacer material separates a portion of the SIS from the first transistor and from the second transistor, and an end surface of the SIS on the second side of the substrate is coplanar with the end surface of the second transistor.
Regarding Claim 16 (from which claims 17-20 depend), a self-aligned interconnect structure (SIS) extending through an entirety of the substrate in a thickness direction, wherein the spacer material separates a portion of the SIS from the first transistor and from the second transistor, and an end surface of the SIS on the second side of the substrate is coplanar with the end surface of the second transistor…
Claims 6-12 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Greene (US 2017/0062325), Purushothaman (US 2015/0054149), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 6 (from which claims 7-12 depend), a self-aligned interconnect structure (SIS) extending through an entirety of the substrate in a thickness direction, wherein the spacer material separates a portion of the SIS from the first transistor and from the second transistor, and an end surface of the SIS on the second side of the substrate is coplanar with the end surface of the second transistor.
Note: if claims 13-15 would also be allowed if rewritten to overcome the 112 rejections above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Greene (US 2017/0062325) discloses (Fig. 2G) a self-aligned interconnect patterning stack 244 on fin transistors 220s.
Greene does not disclose a self-aligned interconnect structure (SIS) extending through an entirety of the substrate in a thickness direction, wherein the spacer material separates a portion of the SIS from the first transistor and from the second transistor, and an end surface of the SIS on the second side of the substrate is coplanar with the end surface of the second transistor.
Purushothaman (US 2015/0054149) discloses (Figs. 8-9) first wafer 4000 and second wafer 7000 is formed on two sides of bonding pads 3200 and 6200 with interconnect structures 1900 and 5000 on either side of the pads. Purushothaman does not disclose a self-aligned interconnect structure (SIS) extending through an entirety of the substrate in a thickness direction, wherein the spacer material separates a portion of the SIS from the first transistor and from the second transistor, and an end surface of the SIS on the second side of the substrate is coplanar with the end surface of the second transistor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
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