Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 16, 2024 has been considered by the Examiner.
Drawings
Seven sheets for formal drawings were filed July 31, 2024 and have been accepted by the Examiner.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Stephens et al. (US 2014/0363120 A1).
Regarding claims 1, 8 and 16, Stephens discloses a method of fabricating a semiconductor package (10 in Fig. 1), comprising: forming a base substrate structure (11 in Fig. 1), having a top surface that includes conductive regions disposed in a dielectric region, the conductive regions coupled to an interconnect structure (paragraph 0021 discloses backplane 11 including dielectric layers formed to cover interconnect features); forming a first die (15), including: forming a photonic device (37 in Fig. 2; paragraph 0023) on a first substrate of the first die, wherein the photonic device includes a waveguide section (305 in Figs. 23-31); forming a first interconnect structure at a first surface of the first die (paragraph 0021 discloses the plurality of dies 12-15 may be implemented as a die stack module, wherein each die is formed with through-silicon vias to provide vertical signal conductors for the die stack; the vias would necessarily reach the top first surface in order to electrically connect to the next die); forming a second interconnect structure at a side surface of an edge of the first die (paragraph 0021 discloses dies 12-15 including edge connectors and/or contacts used to provide electric connections to respective slots 16a-16d on the top surface of the backplane); and bonding the first die sideways on the base substrate structure, with the side surface of the first die bonded to the top surface of the base substrate structure and the first surface of the first die being perpendicular to the top surface of the base substrate structure (Fig. 1; paragraph 0021 discloses each of the dies 12-15 having contacts to provide electrical connection to circuit conductors or electrically conductive devices such as solder balls or flip-chip conductors in the backplane 11).
Still regarding claims 1, 8 and 16, Stephens further discloses removing a portion (312) of the first substrate from a back side to expose a waveguide section (Figs. 23-31; paragraphs 0052-0056 disclose “backside optical TSV structure” 305) at a second surface of the first die. Stephens teaches the claimed invention except for specifically stating the second surface being opposite to the first surface. However, Stephens at paragraph 0064 further discloses optical signals received through opening 321 in a transmission path perpendicular to the lateral plane of the semiconductor wafer structure. Since the die is implemented as a die stack with another die disposed on the top (first) surface, one having ordinary skill in the art would have found it obvious to form the opening at a bottom (second) surface opposite to the first surface, which is also perpendicular to the lateral plane, for the purpose of allowing for optical connection to an external device without increasing the size of the device.
Regarding claims 2, 9 and 17, Stephens further discloses electrically conductive devices such as solder balls used to connect the dies 12-15 with the backplane 11 in paragraph 0021. The proposed combination of Stephens and Uhland teaches the claimed invention except for specifically stating hybrid bonding. However, hybrid bonding is well-known and commonly used in the art of semiconductor devices and as such, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use hybrid bonding to bond the dielectric regions in addition to the conductive regions for the purpose of enhancing the bond.
Regarding claims 3, 10 and 18, Stephens teaches the claimed invention except for specifically stating polishing an edge of the first die to expose the second interconnect structure in the first die. However, polishing a surface before bonding is well-known and commonly used in the art of semiconductor devices and as such, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to polish an edge of the first die to expose the second interconnect structure in the first die for the purpose of ensuring planarization of the surface, leading to enhanced bonding.
Regarding claims 4, 11 and 19, Stephens teaches the claimed invention except for specifically stating coupling an optical fiber to the waveguide section at the back side of the first die. However, coupling an optical fiber to a semiconductor die is well-known and commonly used in the art of semiconductor devices and as such, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to couple an optical fiber to the waveguide section at a back side for the purpose of allowing for optical connection to an external device.
Regarding claim 5, Stephens discloses forming the photonic device (37) comprises forming a laser or optical sensor on the first substrate in paragraph 0023. id crystal moleculesand specifically stating the exposure voltage greater than a
Regarding claim 6, Stephens discloses forming the photonic device (37) comprises bonding a laser or optical sensor on the first substrate in Fig. 1. id crystal moleculesand specifically stating the exposure voltage greater than a
Regarding claims 7 and 12, Stephens discloses the second interconnect structure in the first die is electrically coupled to the interconnect structure of the base substrate structure (paragraph 0021 discloses dies 12-15 including edge connectors and/or contacts used to provide electric connections to respective slots 16a-16d on the top surface of the backplane).
Regarding claim 13, Stephens discloses forming cladding layers (304) surrounding the waveguide section in Figs. 23-31.
Regarding claims 14, 15 and 20, Stephens discloses forming a first conductive region at the side surface of the first die, and bonding the first die sideways to the base substrate structure comprises: bonding the first conductive region at the side surface of the first die to one of the conductive regions of the base substrate structure (paragraph 0021 discloses dies 12-15 including edge connectors and/or contacts used to provide electric connections to respective slots 16a-16d on the top surface of the backplane).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRIS H CHU whose telephone number is (571)272-8655. The examiner can normally be reached on Mon-Fri 9AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached on 571-272-239797. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Any inquiry of a general or clerical nature should be directed to the Technology Center 2800 receptionist at telephone number (571) 272-1562.
Chris H. Chu
/CHRIS H CHU/ Primary Examiner, Art Unit 2874 September 1, 2026
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