SEMICONDUCTOR DEVICE

Application No. 18/792,762

• Filed: Aug 02, 2024
• Priority: Jul 22, 2011 — JP 2011-161383
  • Jul 16, 2012 — continuation of 9136388
  • Sep 11, 2015 — divisional of 10/153,378
  • Oct 18, 2018 — continuation of 10/991,829
  • Feb 02, 2021 — continuation of 12/062,722
• Examiner: PROSTOR, ANDREW VICTOR
• Assignee: Semiconductor Energy Laboratory Co., Ltd.
• OA Round: 1 (Non-Final)

Office Action

Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 13/549867 filed on 02/26/2013.

Status of Claims
Claims 2-13 are pending.
Claims 1 is cancelled.

Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for a patent.

Claim 2-13 are rejected under pre-AIA 35 U.S.C. 102(a) as being anticipated by US 2011/0114945 A1 Yamazaki et al (herein “Yamazaki”).
Regarding Claim 2, Yamazaki discloses:
A semiconductor device (see generally Figs. 1A and 1B showing cross-sectional view of semiconductor device, Figs. 3A-3E showing manufacturing steps of forming oxide semiconductor transistor, and Figs. 4A-4D showing manufacturing steps of forming electrical connection between transistors, reference made to Fig. 1A unless otherwise specified) comprising:
a substrate (#100);
an oxide insulating layer (#138) over the substrate (#100);
an oxide semiconductor layer (#140), a source electrode layer (#142a), and a drain electrode layer (#142b) over and in contact with the oxide insulating layer (#138);
a silicon oxide film (#146) over and in contact with a top surface of the oxide semiconductor layer (#140), a top surface and a side surface of the source electrode layer (#142a), and a top surface and a side surface of the drain electrode layer (#142b);
a first insulating film (#150) over the silicon oxide film (#146); and
a first wiring layer (#154d, #158c) and a second wiring layer (#154e, #158d) over the first insulating film (#150), wherein the oxide semiconductor layer (#140) comprises indium, gallium, and zinc ([0113]-[0116]. [0131]),
wherein the oxide semiconductor layer (#140) comprises a channel formation region (middle portion of #140) of a first transistor (#162),
wherein the first wiring layer (#154d, #158c, #158c) is electrically connected to the source electrode layer (#142a) via a first opening provided in the silicon oxide film (#146) and the first insulating film (#150),
wherein the second wiring layer (#154e, #158d) is electrically connected to the drain electrode layer (#142b) via a second opening provided in the silicon oxide film (#146) and the first insulating film (#150),
wherein the first wiring layer (#154d, #158c, #158c) is electrically connected to a second transistor (#160),
wherein, in a cross-sectional view, the source electrode layer (#142a) is in contact with the top surface and a side surface of the oxide semiconductor layer (#140),
wherein, in the cross-sectional view, the first wiring layer (#154d, #158c, #158c) overlaps with the side surface of the oxide semiconductor layer (#140) and the source electrode layer (#142a),
wherein the oxide semiconductor layer (#140) has a first thickness ([0119], “…The thickness of the oxide semiconductor layer is set in the range of 2 nm to 200 nm, preferably 5 nm to 30 nm.”),
wherein the source electrode layer (#142a) has a second thickness ([0150], “Note that by the oxidation treatment, the oxide regions 143 are formed in part of the source or drain electrode 142a and the source or drain electrode 142b (particularly, portions corresponding to side surfaces thereof)… Note that the oxide regions 143 are sufficiently effective when having a thickness of 5 nm or more (preferably, 10 nm or more).”),
wherein the first wiring layer (#154d, #158c, #158c) has a third thickness (see Fig. 1A),
wherein the first thickness is greater than the second thickness (see [0119] and [0150], range of first thickness is defined as 2nm to 200nm and second thickness is greater than 5nm), and
wherein the third thickness is greater than the first thickness (see Fig. 1A).
Note, the element “a third thickness” as currently claimed does not specify a direction in which the thickness is in reference to. Thus, under the broadest reasonable interpretation the thickness can be interpreted as in a vertical direction with respect to the page, a horizontal direction with respect to the page, or in/out with respect to the page. With respect to the drawings, it appears the only instance where at least a portion of the thickness of the first wiring layer (#465a in Fig. 1E of the instant application) is larger than the thickness of the oxide semiconductor layer (#403 in Fig. 1A of the instant application) is in the vertical direction with respect to the page. Therefore, the claimed element will be interpreted and examined as such.

Regarding Claim 3, Yamazaki discloses:
A semiconductor device (see generally Figs. 1A and 1B showing cross-sectional view of semiconductor device, Figs. 3A-3E showing manufacturing steps of forming oxide semiconductor transistor, and Figs. 4A-4D showing manufacturing steps of forming electrical connection between transistors, reference made to Fig. 1A unless otherwise specified) comprising:
a substrate (#100);
an oxide insulating layer (#138) over the substrate (#100);
an oxide semiconductor layer (#140), a source electrode layer (#142a), and a drain electrode layer (#142b) over and in contact with the oxide insulating layer (#138);
a silicon oxide film (#146) over and in contact with a top surface of the oxide semiconductor layer (#140), a top surface and a side surface of the source electrode layer (#142a), and a top surface and a side surface of the drain electrode layer (#142b);
a first insulating film (#150) over the silicon oxide film (#146); and
a first wiring layer (#154d, #158c) and a second wiring layer (#154e, #158d) over the first insulating film (#150), wherein the oxide semiconductor layer (#140) comprises indium, gallium, and zinc ([0113]-[0116]. [0131]),
wherein the oxide semiconductor layer (#140) comprises a channel formation region (middle portion of #140) of a first transistor (#162),
wherein the first wiring layer (#154d, #158c) is electrically connected to the source electrode layer (#142a) via a first opening provided in the silicon oxide film (#146) and the first insulating film (#150),
wherein the second wiring layer (#154e, #158d) is electrically connected to the drain electrode layer (#142b) via a second opening provided in the silicon oxide film (#146) and the first insulating film (#150),
wherein the first wiring layer (#154d, #158c) is electrically connected to a second transistor (#160),
wherein, in a cross-sectional view, the source electrode layer (#142a) is in contact with the top surface and a side surface of the oxide semiconductor layer (#140),
wherein, in the cross-sectional view, the first wiring layer (#154d, #158c) overlaps with the side surface of the oxide semiconductor layer (#140) and the source electrode layer (#142a),
wherein the oxide semiconductor layer (#140) has a first thickness ([0119], “…The thickness of the oxide semiconductor layer is set in the range of 2 nm to 200 nm, preferably 5 nm to 30 nm.”),
wherein the source electrode layer (#142a) has a second thickness ([0150], “Note that by the oxidation treatment, the oxide regions 143 are formed in part of the source or drain electrode 142a and the source or drain electrode 142b (particularly, portions corresponding to side surfaces thereof)… Note that the oxide regions 143 are sufficiently effective when having a thickness of 5 nm or more (preferably, 10 nm or more).”),
wherein the first wiring layer (#154d, #158c) has a third thickness (see Fig. 1A),
wherein the first thickness is greater than the second thickness (see [0119] and [0150], range of first thickness is defined as 2nm to 200nm and second thickness is greater than 5nm),
wherein the third thickness is greater than the first thickness (see Fig. 1A).
wherein the side surface of the source electrode layer (#142a) has a tapered shape (see tapered/slopes sidewall of source and drain electrode structures in Fig. 1A), and
wherein the oxide semiconductor layer (#140) has an island shape ([0108], Fig. 3B).
Note, the element “a third thickness” as currently claimed does not specify a direction in which the thickness is in reference to. Thus, under the broadest reasonable interpretation the thickness can be interpreted as in a vertical direction with respect to the page, a horizontal direction with respect to the page, or in/out with respect to the page. With respect to the drawings, it appears the only instance where at least a portion of the thickness of the first wiring layer (#465a in Fig. 1E of the instant application) is larger than the thickness of the oxide semiconductor layer (#403 in Fig. 1A of the instant application) is in the vertical direction with respect to the page. Therefore, the claimed element will be interpreted and examined as such.

Regarding Claim 4, Yamazaki discloses:
A semiconductor device (see generally Figs. 1A and 1B showing cross-sectional view of semiconductor device, Figs. 3A-3E showing manufacturing steps of forming oxide semiconductor transistor, and Figs. 4A-4D showing manufacturing steps of forming electrical connection between transistors, reference made to Fig. 1A unless otherwise specified) comprising:
a substrate (#100);
an oxide insulating layer (#138) over the substrate (#100);
an oxide semiconductor layer (#140), a source electrode layer (#142a), and a drain electrode layer (#142b) over and in contact with the oxide insulating layer (#138);
a silicon oxide film (#146) over and in contact with a top surface of the oxide semiconductor layer (#140), a top surface and a side surface of the source electrode layer (#142a), and a top surface and a side surface of the drain electrode layer (#142b);
a first insulating film (#150) over the silicon oxide film (#146); and
a first wiring layer (#154d, #158c) and a second wiring layer (#154e, #158d) over the first insulating film (#150), wherein the oxide semiconductor layer (#140) comprises indium, gallium, and zinc ([0113]-[0116]. [0131]),
wherein the oxide semiconductor layer (#140) comprises a channel formation region (middle portion of #140) of a first transistor (#162),
wherein the first wiring layer (#154d, #158c) is electrically connected to the source electrode layer (#142a) via a first opening provided in the silicon oxide film (#146) and the first insulating film (#150),
wherein the second wiring layer (#154e, #158d) is electrically connected to the drain electrode layer (#142b) via a second opening provided in the silicon oxide film (#146) and the first insulating film (#150),
wherein the first wiring layer (#154d, #158c) is electrically connected to a second transistor (#160),
wherein, in a cross-sectional view, the source electrode layer (#142a) is in contact with the top surface and a side surface of the oxide semiconductor layer (#140),
wherein, in the cross-sectional view, the first wiring layer (#154d, #158c) overlaps with the side surface of the oxide semiconductor layer (#140) and the source electrode layer (#142a),
wherein the oxide semiconductor layer (#140) has a first thickness ([0119], “…The thickness of the oxide semiconductor layer is set in the range of 2 nm to 200 nm, preferably 5 nm to 30 nm.”),
wherein the source electrode layer (#142a) has a second thickness ([0150], “Note that by the oxidation treatment, the oxide regions 143 are formed in part of the source or drain electrode 142a and the source or drain electrode 142b (particularly, portions corresponding to side surfaces thereof)… Note that the oxide regions 143 are sufficiently effective when having a thickness of 5 nm or more (preferably, 10 nm or more).”),
wherein the first wiring layer (#154d, #158c) has a third thickness (see Fig. 1A),
wherein the first thickness is greater than the second thickness ([0119] and [0150], range of first thickness is defined as 2nm to 200nm and second thickness is greater than 5nm),
wherein the third thickness is greater than the first thickness (see Fig. 1A),
wherein the side surface of the source electrode layer (#142a) has a tapered shape (see tapered/slopes sidewall of source and drain electrode structures in Fig. 1A),
wherein the oxide semiconductor layer (#140) has an island shape ([0108], Fig. 3B), and
wherein the oxide semiconductor layer (#140) comprises a c-axis-aligned crystal region ([0131]).
Note, the element “a third thickness” as currently claimed does not specify a direction in which the thickness is in reference to. Thus, under the broadest reasonable interpretation the thickness can be interpreted as in a vertical direction with respect to the page, a horizontal direction with respect to the page, or in/out with respect to the page. With respect to the drawings, it appears the only instance where at least a portion of the thickness of the first wiring layer (#465a in Fig. 1E of the instant application) is larger than the thickness of the oxide semiconductor layer (#403 in Fig. 1A of the instant application) is in the vertical direction with respect to the page. Therefore, the claimed element will be interpreted and examined as such.

Regarding Claim 5, Yamazaki discloses: The semiconductor device according to claim 2,
Yamazaki further discloses:
further comprising:
a gate electrode layer (#148) overlapping with the channel formation region (middle portion of #140) of the first transistor (#162),
wherein the gate electrode layer (#148) has a fourth thickness (see Fig. 1A), and
wherein the fourth thickness is greater than the third thickness (see Fig. 1A).
Note, the element “a fourth thickness” as currently claimed does not specify a direction in which the thickness is in reference to. Thus, under the broadest reasonable interpretation the thickness can be interpreted as in a vertical direction with respect to the page, a horizontal direction with respect to the page, or in/out with respect to the page. With respect to the drawings, it appears the only instance where at least a portion of the thickness of the gate electrode layer (#401 in Fig. 1B of the instant application) is larger than the thickness of the wiring layers (#465a and #465b in Fig. 1E of the instant application) is in the horizontal direction with respect to the page. Therefore, the claimed element will be interpreted and examined as such.

Regarding Claim 6, Yamazaki discloses: The semiconductor device according to claim 3,
Yamazaki further discloses:
further comprising:
a gate electrode layer (#148) overlapping with the channel formation region (middle portion of #140) of the first transistor (#162),
wherein the gate electrode layer (#148) has a fourth thickness (see Fig. 1A), and
wherein the fourth thickness is greater than the third thickness (see Fig. 1A).
Note, the element “a fourth thickness” as currently claimed does not specify a direction in which the thickness is in reference to. Thus, under the broadest reasonable interpretation the thickness can be interpreted as in a vertical direction with respect to the page, a horizontal direction with respect to the page, or in/out with respect to the page. With respect to the drawings, it appears the only instance where at least a portion of the thickness of the gate electrode layer (#401 in Fig. 1B of the instant application) is larger than the thickness of the wiring layers (#465a and #465b in Fig. 1E of the instant application) is in the horizontal direction with respect to the page. Therefore, the claimed element will be interpreted and examined as such.

Regarding Claim 7, Yamazaki discloses: The semiconductor device according to claim 4,
Yamazaki further discloses:
further comprising:
a gate electrode layer (#148) overlapping with the channel formation region (middle portion of #140) of the first transistor (#162),
wherein the gate electrode layer (#148) has a fourth thickness (see Fig. 1A), and
wherein the fourth thickness is greater than the third thickness (see Fig. 1A).
Note, the element “a fourth thickness” as currently claimed does not specify a direction in which the thickness is in reference to. Thus, under the broadest reasonable interpretation the thickness can be interpreted as in a vertical direction with respect to the page, a horizontal direction with respect to the page, or in/out with respect to the page. With respect to the drawings, it appears the only instance where at least a portion of the thickness of the gate electrode layer (#401 in Fig. 1B of the instant application) is larger than the thickness of the wiring layers (#465a and #465b in Fig. 1E of the instant application) is in the horizontal direction with respect to the page. Therefore, the claimed element will be interpreted and examined as such.

Regarding Claim 8, Yamazaki discloses: The semiconductor device according to claim 2,
Yamazaki further discloses:
wherein the oxide semiconductor layer (#140) comprises a dopant ([0075]), and
wherein the dopant is one of phosphorus, arsenic, antimony, boron, aluminum, nitrogen, argon, helium, neon, fluorine, chlorine, and titanium ([0075]).

Regarding Claim 9, Yamazaki discloses: The semiconductor device according to claim 3,
Yamazaki further discloses:
wherein the oxide semiconductor layer (#140) comprises a dopant ([0075]), and
wherein the dopant is one of phosphorus, arsenic, antimony, boron, aluminum, nitrogen, argon, helium, neon, fluorine, chlorine, and titanium ([0075]).

Regarding Claim 10, Yamazaki discloses: The semiconductor device according to claim 4,
Yamazaki further discloses:
wherein the oxide semiconductor layer (#140) comprises a dopant ([0075]), and
wherein the dopant is one of phosphorus, arsenic, antimony, boron, aluminum, nitrogen, argon, helium, neon, fluorine, chlorine, and titanium ([0075]).

Regarding Claim 11, Yamazaki discloses: The semiconductor device according to claim 2,
Yamazaki further discloses:
wherein a composition ratio of gallium in the oxide semiconductor layer (#140) is lower than a composition ratio of zinc in the oxide semiconductor layer ([0116]).

Regarding Claim 12, Yamazaki discloses: The semiconductor device according to claim 3,
Yamazaki further discloses:
wherein a composition ratio of gallium in the oxide semiconductor layer (#140) is lower than a composition ratio of zinc in the oxide semiconductor layer ([0116]).

Regarding Claim 13, Yamazaki discloses: The semiconductor device according to claim 4,
Yamazaki further discloses:
wherein a composition ratio of gallium in the oxide semiconductor layer (#140) is lower than a composition ratio of zinc in the oxide semiconductor layer ([0116]).

Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is [phone]. The examiner can normally be reached M-F 8:00a-4:30p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at [phone]. The fax phone number for the organization where this application or proceeding is assigned is [phone].
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812

Prosecution Timeline

• Aug 02, 2024: Application Filed
• Sep 21, 2026: Non-Final Rejection mailed — §102 (current)