DETAILED ACTION
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims, as mentioned below, of U.S. Patent No. 12082461 Although the claims at issue are not identical, they are not patentably distinct from each other.
For example, claim 1 of current application is corresponding to claim 17 of U.S. Patent No. 12082461. Wherein claim 17 having “a second semiconductor layer between the second gate layer and the first connecting electrode layer; and a third gate layer between the second semiconductor layer and the first connecting electrode layer, the third gate layer including a compensation gate electrode” is inherently corresponding to a claim portion “a second semiconductor layer disposed on the second gate layer; a third gate layer disposed on the second semiconductor layer and including a compensation gate electrode” in Claim 1 of current application.
For example, claim 2 of the current application is corresponding to claim 1 of U.S. Patent No. 12082461.
For example, claim 3 of the current application is corresponding to claim 18 of U.S. Patent No. 12082461.
For example, claim 4 of the current application is corresponding to claim 19 of U.S. Patent No. 12082461.
For example, claim 5 of the current application is corresponding to claim 20 of U.S. Patent No. 12082461.
For example, claim 6 of the current application is corresponding to claim 202of U.S. Patent No. 12082461.
For example, claim 7 of the current application is corresponding to claim 3 of U.S. Patent No. 12082461.
For example, claim 8 of the current application is corresponding to claim 4 of U.S. Patent No. 12082461.
For example, claim 9 of the current application is corresponding to claim 5 of U.S. Patent No. 12082461.
For example, claim 10 of the current application is corresponding to claim 6 of U.S. Patent No. 12082461.
For example, claim 11 of the current application is corresponding to claim 7 of U.S. Patent No. 12082461.
For example, claim 12 of the current application is corresponding to claim 8 of U.S. Patent No. 12082461.
For example, claim 13 of the current application is corresponding to claim 9 of U.S. Patent No. 12082461.
For example, claim 14 of the current application is corresponding to claim 10 of U.S. Patent No. 12082461.
For example, claim 15 of the current application is corresponding to claim 11 of U.S. Patent No. 12082461.
For example, claim 16 of the current application is corresponding to claim 12 of U.S. Patent No. 12082461.
For example, claim 17 of the current application is corresponding to claim 13 of U.S. Patent No. 12082461.
For example, claim 18 of the current application is corresponding to claim 14 of U.S. Patent No. 12082461.
For example, claim 19 of the current application is corresponding to claim 15 of U.S. Patent No. 12082461.
For example, claim 20 of the current application is corresponding to claim 16 of U.S. Patent No. 12082461.
For example, claim 21 of the current application is corresponding to claims 21, 24, 25 of U.S. Patent No. 12082461.
For example, claim 22 of the current application is corresponding to claim 22 of U.S. Patent No. 12082461.
For example, claim 23 of the current application is corresponding to claim 23 of U.S. Patent No. 12082461.
For example, claim 24 of the current application is corresponding to claim 26 of U.S. Patent No. 12082461.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kang et al. (2020/0373369) disclose a display apparatus (for example, see fig. 14)
comprising: a first semiconductor layer (AS1) disposed on a substrate (100); a first gate layer (G1) disposed on the first semiconductor layer (AS1), the first gate layer (G1) is a driving gate electrode; a second gate layer (a conductive layer C2, formed on the first gate G1, functioning as a second gate layer) disposed on the first gate layer (G1) wherein the second gate layer (the conductive layer C2) is a capacitor upper electrode; a first connecting electrode layer (referred to as "CE1" by examiner's annotation shown in fig. 14 below) disposed on the second gate layer (the conductive layer C2, formed on the first gate G1, functioning as a second gate layer), the first connecting electrode layer (CE2) is a transfer wiring; a second connecting electrode layer (referred to as "CE2" by examiner's annotation shown in fig. 14 below) disposed on the first connecting electrode layer (CE1), the second connecting electrode layer (CE1) including a horizontal connection wiring (referred to as "W1" by examiner's annotation shown in fig. 14 below) extending in a first direction (X-direction); and a third connecting electrode layer (an electrode layer 310 functioning as a third connecting electrode layer) disposed on the second connecting electrode layer (CE2), the third connecting electrode layer (310) including a vertical connection wiring (referred to as "W2" by examiner's annotation shown in fig. 14 below) extending in a second direction (Y-direction) that intersects the first direction (X-direction); or
an organic light-emitting diode (OLED); a driving transistor (T1) that controls an amount of current flowing from a first node (310) to the organic light-emitting diode (OLED)in response to a voltage applied to a second node (330), the first node (310) being electrically connected to a driving voltage line (CM); a switching transistor (T2) that inherently transfers a data signal from a data wiring to the first node.
PNG
media_image1.png
590
773
media_image1.png
Greyscale
Allowable Subject Matter
3. Claims 1 - 24 would be allowable if rewritten, or amended, or the filing of a terminal disclaimer to overcome the nonstatutory double patenting rejection, set forth in this Office action.
Claims 1 - 20 are allowable over the prior art of record because none of these references disclose or can be combined to yield the claimed invention such as a second semiconductor layer disposed on the second gate layer; a third gate layer disposed on the second semiconductor layer and including a compensation gate electrode as recited in claim 1.
Claims 21 - 24 are allowable over the prior art of record because none of these references disclose or can be combined to yield the claimed invention such as an initialization transistor that applies an initialization voltage from an initialization voltage line to the second node, in response to a voltage applied to a previous scan line, the initialization transistor including an initialization semiconductor layer disposed on an insulating layer that overlaps a driving semiconductor layer included in the driving transistor; a transfer wiring disposed on an insulating layer that overlaps an initialization gate electrode included in the initialization transistor, the transfer wiring electrically connecting the initialization semiconductor layer to a driving gate electrode included in the driving transistor; a horizontal connection wiring disposed on an insulating layer that overlaps the transfer wiring and extending in a first direction; a vertical connection wiring disposed on an insulating layer that overlaps the horizontal connection wiring and extending in a second direction intersecting the first direction; and the data wiring disposed on the insulating layer as the vertical connection wiring and extending in the second direction as recited in claim 21.
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights