CTNF 18/795,058 CTNF 81308 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Species I in the reply filed on 05/15/2026 is acknowledged. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-9 and 15-25 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Wu et al. (US Pat. 9,177,624) . Regarding claim 1, Fig. 6A and 6B of Wu discloses a memory circuit, comprising: a plurality of memory cells [71 to 7x, Fig. 3] commonly coupled to a word line [WL, Fig. 3]; a word line driver [combination of Mb and Ma] selectively coupled to the word line [WL] and configured to assert the word line to a first voltage [VDD] when coupled to the word line [WL]; an overvoltage generator [60] configured to charge a capacitor [Cbst]; and a memory controller [80, Fig. 3] configured to: couple the word line driver with the word line to assert the word line to the first voltage [at t1, Mb is active to couple the word line driver to WL]; decouple the word line driver from the word line to maintain the word line at the first voltage [at t2, Mb is off to decouple word line driver to WL, but WL voltage maintains at VDD at t2]; couple the overvoltage generator [60] with the capacitor to charge the capacitor [Cbst] to a voltage exceeding the first voltage [at t2, Boost circuit 60 activates to charge Cbst to a voltage higher than the first voltage [VDD + Vdelta]; couple the capacitor [Cbst] with the word line to assert the word line to the voltage in excess of the first voltage [after t3, Cbst at terminal BSTH couples to WL to bost WL voltage to VDD+Vdelta]; and write a data value to one of the plurality of memory cells with the word line driven to the voltage in excess of the first voltage [as discloses in col. 1 line 33 to col. 2 line 20, conventional voltage is insufficient for memory to perform writing operation. Therefore, a boost voltage as shows in Fig. 6 will provide sufficient voltage for the memory device operates normally. Therefore, it is inherent that the boost voltage [VDD+Vdelta] is used to write data value to the memory cells]. Regarding claims 2, 19, 22, and 24 , Fig. 6A and 6B of Wu discloses wherein the memory circuit is configured to: receive an indication of an operating condition comprising an operating temperature, operating voltage [operation voltage as shows in Fig. 6B], or timing parameter; select, based on the operating condition, the voltage [VDD+Vdelta] exceeding the first voltage; and couple the capacitor [Cbst[ with the word line [WL] responsive to the selection of the voltage. Regarding claim 3 , Fig. 6A and 6B of Wu discloses wherein the capacitor [Cbst] comprises a plurality of electrodes couplable with the word line to assert the word line to a plurality of voltages [BSTL and BSTH]. Regarding claim 4 , Fig. 6A and 6B of Wu discloses wherein the memory controller is configured to: select, based on an operating condition of the memory circuit, a first electrode [BSTH] of the plurality of electrodes; and couple the first electrode [BSTH] with the word line [WL]. Regarding claim 5 , Fig. 6B of Wu discloses wherein the memory controller is configured to, according to a predefined timing or slew rate: couple a first electrode [BSTH] of the plurality of electrodes with the word line [WL]; and couple a second electrode [BSTL] of the plurality of electrodes with the word line [WL]. Regarding claims 6 and 25 , Fig. 6B of Wu discloses wherein the capacitor [Cbst] comprises a metal line disposed in a metallization layer of the memory circuit [71 to 7x in Fig. 3]. Regarding claim 7 , Fig. 4 of Wu discloses a second plurality of memory cells [Memory 100, Fig. 4] couplable with a second word line [similar to WL], the word line driver [WL driver 70] selectively coupled to the second word line and configured to assert the second word line to the first voltage; and a second overvoltage generator [Boost circuit] to charge a second capacitor [similar to Cbst] to the voltage exceeding the first voltage. Regarding claim 8 , Fig. 3 of Wu discloses wherein the plurality of memory cells are addressable according to a first state [0] of an address line and the second plurality of memory cells are addressable according to a second state [1] of the address line, opposite from the first state [inherent for memory because memory can stores two opposite states (0 vs 1)]. Regarding claims 9 and 20 , Fig. 3 of Wu discloses wherein the word line is coupled to a second word line driver [70] at a second end [left], opposite from a first end driven by the word line driver. Regarding claim 15 , Fig. 6A and 6B of Wu discloses a method for storing a data value, comprising: driving a word line [WL] to a first voltage by a word line driver [Mb & Ma]; charging, by a first overvoltage generator [60], a capacitor [Cbst] to a second voltage [VDD+VDelta], greater than the first voltage [VDD]; decoupling the word line from the word line driver [at t2, Mb is off]; coupling the capacitor [Cbst] with the word line [WL] to assert the word line to a third voltage [VDD+Vdelta], greater than the first voltage [VDD]; and writing, to a first memory cell coupled to the word line at the third voltage, a data value [as discloses in col. 1 line 33 to col. 2 line 20, conventional voltage is insufficient for memory to perform writing operation. Therefore, a boost voltage as shows in Fig. 6 will provide sufficient voltage for the memory device operates normally. Therefore, it is inherent that the boost voltage [VDD+Vdelta] is used to write data value to the memory cells]. Regarding claim 16, Fig. 3 of Wu discloses herein the capacitor [c1 to cx] comprises a metal line disposed in a metallization layer vertically spaced from a transistor of the first memory cell. Regarding claim 17 , Fig. 4 of Wu discloses wherein the method comprises: charging, by a second overvoltage generator [60], a second capacitor [similar to Cbst] to the second voltage [VDD+Vdelta]; coupling the second capacitor with a second word line [similar to WL] to assert the second word line to the third voltage [VDD+VDelta]; and writing, to a second memory cell coupled to the word line at the third voltage, a second data value, wherein: the first memory cell and the second memory cell are cells of a same array [Memory 100]; the word line is coupled to a first plurality of memory cells of the array comprising the first memory cell [71], and connected to a first address line and not to a second address line; and the second word line [second row] is coupled to a second plurality of memory cells of the array, the second plurality of memory cells comprising the second memory cell and connected to the second address line and not to the first address line [different row has different address]. Regarding claim 18 , Fig. 6A and 6B of Wu discloses wherein the capacitor comprises: a first electrode [BSTL] at the third voltage [VDD]; and a second electrode [BSTH] at a fourth voltage [VDD + VDelta], higher than the third voltage [VDD]. Regarding claim 21 , Fig. 6A and 6B of Wu discloses a circuit, comprising: a word line driver [Mb & Ma] selectively coupled to a word line [WL] and configured to assert the word line to a first voltage [VDD] when coupled to the word line; an overvoltage generator [60] configured to charge a capacitor [Cbst]; and a memory controller [80, Fig. 4] configured to: couple the word line driver [Mb] with the word line [WL] to assert the word line to the first voltage [VDD, at t1]; decouple [at t2, Mb is off] the word line driver from the word line to maintain the word line at the first voltage [WL remains at VDD at t2]; couple the overvoltage generator [60] with the capacitor [Cbst] to charge the capacitor to a second voltage [VDD + VDelta]; and couple the capacitor [at BSTH] with the word line [WL] to assert the word line to the second voltage [after t3]. Regarding claim 23 , Fig. 6A of Wu discloses wherein the capacitor comprises a plurality of electrodes [BSTL and BSTH]couplable with the word line [WL] to assert the word line to a plurality of voltages. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHAN TRAN/Primary Examiner, Art Unit 2825 Application/Control Number: 18/795,058 Page 2 Art Unit: 2825 Application/Control Number: 18/795,058 Page 3 Art Unit: 2825 Application/Control Number: 18/795,058 Page 4 Art Unit: 2825 Application/Control Number: 18/795,058 Page 5 Art Unit: 2825 Application/Control Number: 18/795,058 Page 6 Art Unit: 2825 Application/Control Number: 18/795,058 Page 7 Art Unit: 2825 Application/Control Number: 18/795,058 Page 8 Art Unit: 2825
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