DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation “the indentation” in line 7. There is insufficient antecedent basis for this limitation in the claim. For the purposes of this office action, the limitation “the indentation” will be considered equivalent of “the indentation first trench”
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 12757692. Although the claims at issue are not identical, they are not patentably distinct from each other because.
Claim 1 is rejected in view of claims 1, 5 and 6 of US Patent 12757692, as all limitations of claim 1 of present application are recited in the above cited claims of US Patent 12757692.
Similarly, claim 2 is rejected in view of claim 2 of US Patent 12757692
Similarly, claim 3 is rejected in view of claim 3 of US Patent 12757692
Similarly, claim 4 is rejected in view of claim 4 of US Patent 12757692
Similarly, claim 5 is rejected in view of claims 7, 10 and 11 of US Patent 12757692
Similarly, claim 6 is rejected in view of claim 8 of US Patent 12757692
Similarly, claim 7 is rejected in view of claim 9 of US Patent 12757692
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20130045562), hereinafter Liu, in view of Li (US 20180090336), hereinafter Li.
Regarding claim 1, Liu (US 20130045562) (see Figure 4 and it’s markup provided below) teaches a semiconductor device (para 1), comprising:
a substrate (10, described as "substrate 10" in para 23);
an indentation (IN, it comprises surfaces IN-B and IN-S, see markup of Figure 4) inwardly positioned in the substrate (10) and comprising a bottom surface (IN-B, see markup of Figure 4) and two sidewalls (IN-S, see markup of Figure 4); and
a catalytic conductive layer (20, described in para 48 as "metal nanoparticles 20" that are comprised of "Ag" or "Au") positioned on the bottom surface (IN-B) of the indentation.
Although from Figure 4 it appears that bottom surface (IN-B) of the indentation and a top surface (10-T, see markup of Figure 4) of the substrate are parallel to each other, and the two sidewalls (IN-S) of the indentation are substantially vertical (as required by claim 1), Liu does not specifically state that the bottom surface (IN-B) of the indentation and a top surface (10-T, see markup of Figure 4) of the substrate (10) are parallel to each other; and the two sidewalls (IN-S) of the indentation (IN) are substantially vertical (best seen in Figure 4). Further, Liu does not teach wherein the catalytic conductive layer comprises “titanium nitride”.
Li, which also teaches that a semiconductor device having a substrate with indentations (para 43 and 50) and a catalytic conductive layer (such as gold – see para 20 and 5), further teaches it is known in the art to be suitable for producing high-aspect ratio etched features (para 20), although it has some limitations such as introduction of deep-level defects (para 20), and that using an alternate catalytic conductive layer that comprises titanium nitride can prevent the deep-level defects that may be formed when gold is used (para 48, also see para 5 and 20)
It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Liu so that the indentation formed has a high aspect ratio with minimal tapering of vertical surfaces (para 58 of Li), i.e. a structure where the bottom surface (IN-B) of the indentation and a top surface (10-T, see markup of Figure 4) of the substrate (10) are parallel to each other; and the two sidewalls (IN-S) of the indentation (IN) are substantially vertical (best seen in Figure 4); and wherein the catalytic conductive layer comprises “titanium nitride”. The ordinary artisan would have been motivated to modify Liu for at least the purpose of using an etching configuration with a known catalyst such as gold (para 5 and 20 of Li, and para 48 of Liu) for forming high aspect ratio indentations, while using alternate catalysts such as TiN when limitations such as deep-level defects are not acceptable (para 20 of Li).
Still further, Liu does not teach wherein “a crystal orientation of the substrate is <100>, <110>, or <111>”. However, Liu discloses that the substrate (10) may be p-type or n-type having a surface which are either front side surface of single-crystalline silicon substrate or back side surface of the single-crystalline silicon substrate 10 (para 26). Given front side (or back side) surface of a single-crystalline substrate is one the major crystallographic planes, and <100>, <110>, or <111> are Miller indices corresponding to major crystallographic planes, it would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Liu so that a crystal orientation of the single crystal substrate corresponds to one of the major crystallographic planes. The ordinary artisan would have been motivated to modify Liu for at least the purpose of using a major crystallographic plane such as <100>, <110>, or <111> depending on type of device to be fabricated on the substrate.
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Regarding claim 2, Liu (see Figure 4 and it’s markup) teaches the semiconductor device of claim 1, wherein the catalytic conductive layer comprises silver, gold, cobalt, chromium, copper, iron, hafnium, iridium, manganese, molybdenum, palladium, platinum, rubidium, rhenium, rhodium, tantalum, titanium, vanadium, tungsten, zinc, or zirconium (i.e. Ti that comprises the TiN, as explained for claim 1; also para 48 of Liu describes 20 as comprised of "Ag" or "Au").
Regarding claim 3, Liu teaches the semiconductor device of claim 2, wherein the substrate (10) comprises silicon, germanium, silicon germanium, silicon carbon, silicon germanium carbon, gallium, gallium arsenide, indium arsenide, or indium phosphorus {para 23 describes 10 as "silicon substrate 10"}.
Regarding claim 4, Liu teaches the semiconductor device of claim 3, but is silent about aspect ratio; i.e. does not teach “an aspect ratio of the indentation is between about 4:1 and about 12:1”. Li, which also teaches that a semiconductor device having a substrate with indentations (para 43 and 50) and a catalytic conductive layer (such as gold – see para 20 and 5) is known in the art to be suitable for producing high-aspect ratio etched features (para 20), although it has some limitations such as introduction of deep-level defects (para 20). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Liu so that the indentation formed has a high aspect ratio, such as “an aspect ratio of the indentation is between about 4:1 and about 12:1”. The ordinary artisan would have been motivated to modify Liu for at least the purpose of using an etching configuration with a known catalyst such as gold (para 5 and 20 of Li, and para 48 of Liu) for forming high aspect ratio indentations, while using alternate catalysts such as TiN when limitations such as deep-level defects are not acceptable (para 20 of Li).
Regarding claim 5, Liu (US 20130045562) (see Figure 4 and it’s markup provided below) teaches a semiconductor device (para 1), comprising:
a substrate (10, described as "substrate 10" in para 23);
a first trench (IN, it comprises surfaces IN-B and IN-S, see markup of Figure 4) inwardly positioned in the substrate (10) and comprising a bottom surface (IN-B, see markup of Figure 4) and two sidewalls (IN-S, see markup of Figure 4); and
a catalytic conductive layer (20, described in para 48 as "metal nanoparticles 20" that are comprised of "Ag" or "Au") positioned on the bottom surface (IN-B) of the first trench
Although from Figure 4 it appears that bottom surface (IN-B) of the first trench and a top surface (10-T, see markup of Figure 4) of the substrate are parallel to each other, and the two sidewalls (IN-S) of the first trench are substantially vertical (as required by claim 1), Liu does not specifically state that the bottom surface (IN-B) of the first trench and a top surface (10-T, see markup of Figure 4) of the substrate (10) are parallel to each other; and the two sidewalls (IN-S) of the first trench (IN) are substantially vertical (best seen in Figure 4). Further, Liu does not teach wherein the catalytic conductive layer comprises “titanium nitride”.
Li, which also teaches that a semiconductor device having a substrate with first trench (para 43 and 50) and a catalytic conductive layer (such as gold – see para 20 and 5), further teaches it is known in the art to be suitable for producing high-aspect ratio etched features (para 20), although it has some limitations such as introduction of deep-level defects (para 20), and that using an alternate catalytic conductive layer that comprises titanium nitride can prevent the deep-level defects that may be formed when gold is used (para 48, also see para 5 and 20)
It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Liu so that the first trench formed has a high aspect ratio with minimal tapering of vertical surfaces (para 58 of Li), i.e. a structure where the bottom surface (IN-B) of the first trench and a top surface (10-T, see markup of Figure 4) of the substrate (10) are parallel to each other; and the two sidewalls (IN-S) of the first trench (IN) are substantially vertical (best seen in Figure 4); and wherein the catalytic conductive layer comprises “titanium nitride”. The ordinary artisan would have been motivated to modify Liu for at least the purpose of using alternate catalyst such as TiN for locations that have features that are high aspect ratio etches while still avoiding limitations such as deep-level defects are not acceptable (para 20 of Li).
Still further, Liu does not teach wherein “a crystal orientation of the substrate is <100>, <110>, or <111>”. However, Liu discloses that the substrate (10) may be p-type or n-type having a surface which are either front side surface of single-crystalline silicon substrate or back side surface of the single-crystalline silicon substrate 10 (para 26). Given front side (or back side) surface of a single-crystalline substrate is one the major crystallographic planes, and <100>, <110>, or <111> are Miller indices corresponding to major crystallographic planes, it would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Liu so that a crystal orientation of the single crystal substrate corresponds to one of the major crystallographic planes. The ordinary artisan would have been motivated to modify Liu for at least the purpose of using a major crystallographic plane such as <100>, <110>, or <111> depending on type of device to be fabricated on the substrate.
Still further, Liu is silent about aspect ratio; i.e. does not teach “an aspect ratio of the first trench is between about 4:1 and about 12:1”. Li, which also teaches that a semiconductor device having a substrate with first trench (para 43 and 50) and a catalytic conductive layer (such as gold – see para 20 and 5) is known in the art to be suitable for producing high-aspect ratio etched features (para 20), although it has some limitations such as introduction of deep-level defects (para 20). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Liu so that the first trench formed has a high aspect ratio, such as “an aspect ratio of the first trench is between about 4:1 and about 12:1”. The ordinary artisan would have been motivated to modify Liu for at least the purpose of using an etching configuration with a known catalyst such as gold (para 5 and 20 of Li, and para 48 of Liu) for forming high aspect ratio indentations, while using alternate catalysts such as TiN when limitations such as deep-level defects are not acceptable (para 20 of Li).
Regarding claim 6, Liu teaches the semiconductor device of claim 5, wherein the catalytic conductive layer (20) comprises silver, gold, cobalt, chromium, copper, iron, hafnium, iridium, manganese, molybdenum, palladium, platinum, rubidium, rhenium, rhodium, tantalum, titanium, vanadium, tungsten, zinc, or zirconium (para 48 describes 20 as "metal nanoparticles 20" that are comprised of "Ag" or "Au").
Regarding claim 7, Liu teaches the semiconductor device of claim 5, wherein the substrate (10) comprises silicon, germanium, silicon germanium, silicon carbon, silicon germanium carbon, gallium, gallium arsenide, indium arsenide, or indium phosphorus {para 23 describes 10 as "silicon substrate 10"}.
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892
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