DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 9 and 15.
b. Pending: 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuroki PG PUB 20100115324 (hereinafter Kuroki), in view of Hofmann PG PUB 20090031155 (hereinafter Hofmann).
Regarding independent claim 1, Kuroki teaches an integrated circuit, comprising:
a data interface (11 in figures 2 or 3 of Kuroki, [0038] of Kuroki, “…memory interface 11 is connected to the memory 5 through transmission lines. The transmission lines are configured so as to properly perform data communication between the memory 5 and the memory interface 11…”) to communicate a plurality of data signals (DQ in figure 3 of Kuroki) with at least one integrated circuit (5 in figure 3 of Kuroki) via a data channel (14 in figure 3 of Kuroki, [0039], “…data transmission line 14 transfers a data signal DQ between the memory 5 and the memory interface 11…”) and synchronized using strobe signals (DQS in figure 3 of Kuroki), each respective data signal of the plurality of data signals to be deserialized (24 in figure 3 of Kuroki, [0043] of Kuroki, “…memory interface 11 includes a delay detecting circuit 18, a system clock synchronizing circuit 19, a serial/parallel converting circuit 24, a parallel/serial converting circuit 25…”, [0046], “…The serial/parallel converting circuit 24 converts the data signal IDQ (serial data) transmitted from the memory 5 into parallel data and supplies the parallel data to the system clock synchronizing circuit 19…”), by the data channel, into a plurality of deserialized data signals communicated via parallel data interconnections (connections between 24 and 19 in figure 3) that are each operated at a lower data rate (any serial-to-parallel conversion necessarily results in lower per line data rate) than the respective data signal of the plurality of data signals, the plurality of deserialized data signals associated with each respective data signal of the plurality of data signals to be serialized (25 in figure 3, [0047], “…parallel/serial converting circuit 25 converts parallel data transmitted from the logic circuit 28 into a data signal ODQ of serial data…”), by the data channel, into a reconstruction of the respective data signal of the plurality of data signals and communicated to the at least one integrated circuit (5 in figure 3);
strobe calibration circuitry (18 in figure 3 of Kuroki, [0013] of Kuroki, “…delay detecting circuit provided at a front stage to the system clock synchronizing circuit and configured to detect a transmission delay from the clock signal supply buffer to the data strobe buffer…”) to calibrate at least one of the strobe signals to produce correct deserializations, by the data channel, of the plurality of data signals, and to produce, by the data channel, correct reconstructions of the plurality of data signals ([0013] of Kuroki, “…delay detecting circuit generates a phase difference data indicating the transmission delay based on a difference between a phase of the system clock signal and a phase of the data strobe signal outputted from the data strobe buffer, and supplies the phase difference data to the system clock synchronizing circuit… system clock synchronizing circuit generates a read clock signal by shifting the system clock signal based on the phase difference data, and controls a supply timing at which the data is supplied to the logic circuit, based on the read clock signal…”).
But Kuroki does not teach circuitry to provide at least one supply voltage to be used by the data channel.
However, Hofmann teaches adaptive voltage scaling in response to timing characteristic of critical paths ([0007]/[0009] of Hofmann, “…During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths… a voltage is adjusted based on a measurement of the emulated critical path delay…”)
Kuroki teaches precise timing alignment for strobe-synchronized data channels, while Hofmann teaches adjusting supply voltage to meet timing constrains of critical paths. A person of ordinary skill in the art would have been motivated to combine these teachings to optimize power consumption of Kuroki’s timing-critical data channel circuitry while preserving correct deserialization and reconstruction, yielding predictable results. It would have been obvious to apply Hofmann’s adaptive voltage provisioning to Kuroki’s data channel circuitry to trade off power consumption and delay while maintaining correct strobe -based timing, since both references address timing-critical data paths.
Regarding claim 2, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 1, wherein the data channel is to receive, from the integrated circuit (5 in figure 3 of Kuroki), a first power supply voltage and a second power supply voltage (Kuroki teaches a memory interface including multiple circuit blocks (e.g., clock buffer, data strobe buffer, serial/parallel conversion circuit, logic circuit), each powered by supply voltages provided within integrated circuit environment ([0043]-[0048], figure 3), Kuroki further teaches supplying operation voltages to interface circuits used for data transmission and reception. Hofmann explicitly teaches in [0007]-[0009] providing multiple supply voltages to different circuit domains and adjusting operating voltages supplied to function modules. It would have been obvious to provide a first and second power supply voltage to the data channel of Kuroki, as taught by Hofmann, to support different operating conditions and power optimization for different circuit portions).
Regarding claim 3, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 2, wherein the first power supply voltage is used by data channel circuitry that communicates deserialized versions of the plurality of data signals via the parallel data interconnections (Kuroki teaches a serial/parallel converting circuit 24 that outputs parallel data after deserialization and communicate such data via internal parallel data paths, Hofmann teaches powering different functional blocks with selected supply voltages based on their operation and timing requirements. It would have been obvious to apply a first supply voltage to the serial/parallel data circuit of Kuroki).
Regarding claim 4, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 3, further comprising: supply voltage calibration circuitry to adjust the first power supply voltage to tradeoff power consumption by the data channel and delay through the data channel (Kuroki teaches delay detection, timing calibration, and phase adjustment circuitry used to control read timing and data delivery, Hofmann teaches adaptive voltage scaling and calibration of supply voltage to trade off power consumption versus timing delay, it would have been obvious to incorporate Hofmann’s voltage calibration techniques into Kuroki’s calibrated interface to optimize power and delay).
Regarding claim 5, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 2, wherein the second power supply voltage is used by data channel circuitry that performs deserialization and data channel circuitry that performs serialization (Kuroki teaches both serialization and deserialization circuitry, Hofmann teaches applying different operating voltages to different circuitry and adjusting such voltages based on performance need).
Regarding claim 6, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 2, wherein the first power supply voltage is used by data channel circuitry that communicates deserialized versions of the plurality of data signals via the parallel data interconnections, and wherein the second power supply voltage is used by data channel circuitry that performs deserialization and data channel circuitry that performs serialization (Kuroki teaches in figure 3 a serial/parallel converting circuit 24 and parallel/serial converting circuit 25, Hofmann teaches to allocate different supply voltages to different functional blocks).
Regarding claim 7, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 6, wherein the first power supply voltage and the second power supply voltage are independent of a third power supply voltage used by the data interface (Kuroki teaches multiple functional circuits within memory interface, implying separate power domains for interface logic and other system components. Hofmann teaches to allocate different supply voltages to different functional blocks).
Regarding claim 8, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 1, wherein the integrated circuit is a controller and a first one the at least one integrated circuit is a memory device (Kuroki teaches a memory interface positioned between a controller/logic circuit and a memory device, [0006], “…a memory interface is provided between the semiconductor memory device and a CPU…”)
Regarding independent claim 9, the combination of Kuroki and Hofmann teaches an integrated circuit (figures 2, 3), comprising:
a first data interface to communicate a plurality of bidirectional data signals with a first integrated circuit synchronized using strobe signals received from the first integrated circuit (Kuroki teaches a data transmitting/receiving circuit including data buffer 21, 22 and data strobe buffer (22-1, 22-2) that support bidirectional data transfer between the memory interface and memory device, synchronized using data strobe signal, [0042], “…data transmitting/receiving circuit 17 includes a first data buffer 17-1 and a second data buffer 17-2. The first data buffer 17-1 supplies the data signal DQ from the memory 5 to the memory interface 11 through the data transmission line 14. The second data buffer 17-2 supplies the data signal DQ from the memory interface 11 to the memory 5 through the data transmission line 14...”);
deserialization circuitry (24 in figure 3 of Kuroki, [0046], “…serial/parallel converting circuit 24 converts the data signal IDQ (serial data) transmitted from the memory 5 into parallel data and supplies the parallel data to the system clock synchronizing circuit 19…”) to deserialize each respective data signal of the plurality of bidirectional data signals into a plurality of deserialized data signals to be communicated via parallel data interconnections of the integrated circuit that are each operated at a lower data rate than the respective data signal of the plurality of bidirectional data signals;
serialization circuitry (25 in figure 3, [0047], “…parallel/serial converting circuit 25 converts parallel data transmitted from the logic circuit 28 into a data signal ODQ of serial data…”) to serialize each of the plurality of deserialized data signals into a respective reconstruction of the respective data signal of the plurality of bidirectional data signals;
a second data interface to communicate, with a second integrated circuit, respective reconstructions of the respective data signals of the plurality of bidirectional data signals (Kuroki teaches communication between memory interface circuit and logic circuit/system component via reconstructed data signals, including read data supply to logic circuitry in synchronization with a read clock, [0013] of Kuroki, “…supply a data read from the memory to a logic circuit in synchronization with the system clock signal…”, therefore, Kuroki teaches a second data interface communicating reconstructed data signals with another integrated circuit);
strobe calibration circuitry (18 in figure 3 of Kuroki, [0013] of Kuroki, “…delay detecting circuit provided at a front stage to the system clock synchronizing circuit and configured to detect a transmission delay from the clock signal supply buffer to the data strobe buffer…”) to, based on first information received from the first integrated circuit, calibrate at least one of the strobe signals to produce correct deserializations of the plurality of bidirectional data signals, and to produce correct reconstructions of the plurality of bidirectional data signals; and
circuitry to receive, from the first integrated circuit, a first power supply voltage and a second power supply voltage (Hofmann teaches supplying and controlling multiple supply voltages to different power domains based on performance and timing requirements, [0007]-[0009] of Hofmann, “…voltage supplies power to a power domain associated with the plurality of critical paths…a voltage is adjusted based on a measurement of the emulated critical path delay…”).
Regarding claim 10, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 9, wherein the first power supply voltage is used by circuitry that communicates deserialized versions of the plurality of bidirectional data signals via the parallel data interconnections (Kuroki teaches a serial/parallel converting circuit 24 that outputs parallel data after deserialization and communicate such data via internal parallel data paths, Hofmann teaches powering different functional blocks with selected supply voltages based on their operation and timing requirements. It would have been obvious to apply a first supply voltage to the serial/parallel data circuit of Kuroki).
Regarding claim 11, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 10, further comprising: supply voltage calibration circuitry to adjust the first power supply voltage to tradeoff power consumption by the integrated circuit and delay through the integrated circuit (Kuroki teaches delay detection, timing calibration, and phase adjustment circuitry used to control read timing and data delivery, Hofmann teaches adaptive voltage scaling and calibration of supply voltage to trade off power consumption versus timing delay, it would have been obvious to incorporate Hofmann’s voltage calibration techniques into Kuroki’s calibrated interface to optimize power and delay).
Regarding claim 12, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 10, wherein the second power supply voltage is used by the deserialization circuitry and the serialization circuitry (Kuroki teaches both serialization and deserialization circuitry, Hofmann teaches applying different operating voltages to different circuitry and adjusting such voltages based on performance need).
Regarding claim 13, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 12, wherein the first power supply voltage and the second power supply voltage are independent of a third power supply voltage used by the first data interface and the second data interface (Kuroki teaches multiple functional circuits within memory interface, implying separate power domains for interface logic and other system components. Hofmann teaches to allocate different supply voltages to different functional blocks).
Regarding claim 14, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 9, wherein the first integrated circuit is a controller and the second integrated circuit is a memory device (Kuroki teaches a memory interface positioned between a controller/logic circuit and a memory device, [0006], “…a memory interface is provided between the semiconductor memory device and a CPU…”)
Regarding independent claim 15, the combination of Kuroki and Hofmann teaches an integrated circuit, comprising:
a data interface (11 in figures 2 or 3 of Kuroki, [0038] of Kuroki, “…memory interface 11 is connected to the memory 5 through transmission lines. The transmission lines are configured so as to properly perform data communication between the memory 5 and the memory interface 11…”) to communicate a plurality of bidirectional data signals (DQ in figure 3 of Kuroki) with another integrated circuit (5 in figure 3 of Kuroki) via a data channel integrated circuit (14 in figure 3 of Kuroki, [0039], “…data transmission line 14 transfers a data signal DQ between the memory 5 and the memory interface 11…”), the communication of the plurality of bidirectional data signals via the data interface to by synchronized by strobe signals (DQS in figure 3 of Kuroki), the data channel integrated circuit to deserialize, using deserialization circuitry (24 in figure 3 of Kuroki, [0043] of Kuroki, “…memory interface 11 includes a delay detecting circuit 18, a system clock synchronizing circuit 19, a serial/parallel converting circuit 24, a parallel/serial converting circuit 25…”, [0046], “…The serial/parallel converting circuit 24 converts the data signal IDQ (serial data) transmitted from the memory 5 into parallel data and supplies the parallel data to the system clock synchronizing circuit 19…”), each respective data signal of the plurality of bidirectional data signals into a plurality of deserialized data signals, the data channel integrated circuit to communicate, via parallel data interconnections that are each operated at a lower data rate than the respective data signal of the plurality of bidirectional data signals, the plurality of deserialized data signals to serialization circuitry (25 in figure 3 of Kuroki, [0047] of Kuroki, “…parallel/serial converting circuit 25 converts parallel data transmitted from the logic circuit 28 into a data signal ODQ of serial data…”), the serialization circuitry to reconstruct each of the respective data signals of the plurality of bidirectional data signals and communicate reconstructed versions of each of the respective data signals of the plurality of bidirectional data signals to the another integrated circuit;
strobe calibration circuitry (18 in figure 3 of Kuroki, [0013] of Kuroki, “…delay detecting circuit provided at a front stage to the system clock synchronizing circuit and configured to detect a transmission delay from the clock signal supply buffer to the data strobe buffer…”) to calibrate at least one of the strobe signals to produce correct deserializations by the deserialization circuitry and to produce correct reconstructed versions of the plurality of bidirectional data signals by the serialization circuitry ([0013] of Kuroki, “…delay detecting circuit generates a phase difference data indicating the transmission delay based on a difference between a phase of the system clock signal and a phase of the data strobe signal outputted from the data strobe buffer, and supplies the phase difference data to the system clock synchronizing circuit… system clock synchronizing circuit generates a read clock signal by shifting the system clock signal based on the phase difference data, and controls a supply timing at which the data is supplied to the logic circuit, based on the read clock signal…”); and
circuitry to provide at least one supply voltage to be used by data channel integrated circuit (Hofmann teaches supplying and controlling multiple supply voltages to different power domains based on performance and timing requirements, [0007]/[0009] of Hofmann, “…During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths… a voltage is adjusted based on a measurement of the emulated critical path delay…”)
Regarding claim 16, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 15, wherein the data channel integrated circuit is to receive, from the integrated circuit, a first power supply voltage and a second power supply voltage (Kuroki teaches multiple functional circuits within memory interface, implying separate power domains for interface logic and other system components. Hofmann teaches to allocate different supply voltages to different functional blocks).
Regarding claim 17, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 16, wherein the first power supply voltage is used by the data channel integrated circuit to power circuitry that communicates deserialized versions of the plurality of bidirectional data signals via the parallel data interconnections (Kuroki teaches a serial/parallel converting circuit 24 that outputs parallel data after deserialization and communicate such data via internal parallel data paths, Hofmann teaches powering different functional blocks with selected supply voltages based on their operation and timing requirements. It would have been obvious to apply a first supply voltage to the serial/parallel data circuit of Kuroki).
Regarding claim 18, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 17, further comprising: supply voltage calibration circuitry to adjust the first power supply voltage to tradeoff power consumption by the data channel integrated circuit and delay through the data channel integrated circuit (Kuroki teaches delay detection, timing calibration, and phase adjustment circuitry used to control read timing and data delivery, Hofmann teaches adaptive voltage scaling and calibration of supply voltage to trade off power consumption versus timing delay, it would have been obvious to incorporate Hofmann’s voltage calibration techniques into Kuroki’s calibrated interface to optimize power and delay).
Regarding claim 19, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 16, wherein the second power supply voltage is used by the data channel integrated circuit to power the deserialization circuitry and the serialization circuitry (Kuroki teaches both serialization and deserialization circuitry, Hofmann teaches applying different operating voltages to different circuitry and adjusting such voltages based on performance need).
Regarding claim 20, the combination of Kuroki and Hofmann teaches the integrated circuit of claim 15, wherein the integrated circuit is a controller and the another integrated circuit is a memory device (Kuroki teaches a memory interface positioned between a controller/logic circuit and a memory device, [0006], “…a memory interface is provided between the semiconductor memory device and a CPU…”)
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824