DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “Semiconductor Structure Including Buried Bit Line Structures With Bottom Ends at Different Levels”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin (US 2009/0085083 A1).
Regarding claims 1-10:
re claim 1, Shin discloses a semiconductor structure, comprising:
a base structure 1055/105/124;
a first bit line structure 120c (see “first bit line structure” in Fig. 2 and Exhibit A above) buried in the base structure;
a spacer (see “spacer” in Exhibit A) disposed around the first bit line structure; and
a second bit line structure 120c (see “second bit line structure” in Fig. 2 and Exhibit A) buried in the base structure, wherein a maximum width (see “W1” in Exhibit A) of the first bit line structure is less than a maximum width (see “W2” in Exhibit A) of the second bit line structure;
wherein a bottom end of the first bit line structure is not level with a bottom end of the second bit line structure (see “bottom end” in Exhibit A);
re claim 2, the semiconductor structure of claim 1, wherein the base structure includes a base portion and a plurality of active areas 102 (Figs. 1, [0027]) in the base portion, wherein the first bit line structure is disposed between the plurality of active areas (see active areas “2” and “3” in Exhibit B above), and electrically insulated with the plurality of active areas, wherein the second bit line structure is electrically connected to the plurality of active areas (i.e., the bit line 136 [0030] connected to active areas “2” and “3” is electrically insulated from the bit line 136 connected to active area “1”, Exhibit B);
re claim 3, the semiconductor structure of claim 2, wherein the plurality of active areas include a first active area (see “2” in Exhibit B), a second active area (see “3” in Exhibit B) and a third active area (see “1” in Exhibit B), wherein the first bit line structure is disposed between the first active area and the second active area, and electrically insulated with the first active area and the second active area, wherein the second bit line structure is electrically connected to the third active area (see both “electrically connected” in Exhibit B);
re claim 4, the semiconductor structure of claim 2, wherein the first bit line structure and the second bit line structure laterally overlap the plurality of active areas (see Fig. 2 and Exhibit B, wherein the first and second bit line structures laterally overlap active areas 102);
re claim 5, the semiconductor structure of claim 2, wherein a plurality of top surfaces of the plurality of active areas are not aligned with each other (i.e., as viewed in the plan view of Fig. 1, the top surfaces of the active areas “1”, “2”, and “3” are not aligned);
re claim 6, the semiconductor structure of claim 2, wherein at least one of the plurality of active areas defines an indentation recessed from a top surface of the at least one of the plurality of active areas and a lateral surface of the at least one of the plurality of active areas (see “recess and indentation…” Exhibit B);
re claim 7, the semiconductor structure of claim 6, wherein the first bit line structure is disposed in the indentation (see where “first bit line structure” is located in “recess and indentation…” Exhibit B);
re claim 8, the semiconductor structure of claim 2, wherein the maximum width of the first bit line structure and the maximum width of the second bit line structure are greater than a width of one of the plurality of active areas (i.e., in Fig. 2, a maximum width of one active area in a horizontal direction is less than both the widths of the first and second bit line structures);
re claim 9, the semiconductor structure of claim 1, wherein the second bit line structure is free from being surrounded by a spacer (i.e., the “spacer” shown in Exhibit A does not surround the second bit line structure);
re claim 10, the semiconductor structure of claim 1, wherein the first bit line structure is a passing bit line structure, and the second bit line structure is an active bit line structure (i.e., each of the bit lines connected to each of the first and second bit line structures can be a passing bit line or an active bit line depending on which active region is referenced).
Therefore, Shin anticipates claims 1-10.
Allowable Subject Matter
Claims 11-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 11-20 are allowed primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination are recited in independent claim 11: a bit line structure disposed in the base portion and under the cell contact, wherein the bit line structure is electrically insulated from the first active area.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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