Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species I, Sub-species A, sub-sub-species 1, claims 1-13, 16-17, 21-25 in the reply filed on 09/03/2026 is acknowledged. The traversal is on the ground(s) for sub-sub-species 1 vs. 2 which is found persuasive and therefore all claims 1-13, 16-17, 21-25 are considered for examination purpose.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-11, 17, 21-25 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 21 recite “..plurality of frontside interconnect structures coupled to access transistors of the plurality of memory cells” is indefinite as it can be interpreted as there is nothing in between for direct connection which is not disclosed rather another frontside interconnect structure is present in between Claim language like “wherein the first frontside interconnect structure is coupled to gate terminals of access transistors of the plurality of first memory cells through another one of the plurality of frontside interconnect structures” is suggested.
Claims 2-11, 22-25 are also rejected being dependent on rejected claims 1 and 21.
Claim 17 recites “..respective gate terminals of the plurality of memory cells” is indefinite. As shown in Fig. 2, it should be respective gate terminals of the plurality of access transistors.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-13, 16-17, 21-25 are rejected under 35 U.S.C. 103 as being obvious over Arslan et al (US 2020/0411524 A1) in view of Liaw et al (US 2017/0110182 A1).
Regarding claims 1, 12, 21: Arslan teaches in Fig. 1(a) -1 (c) about a memory device, comprising:
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a plurality of first memory cells 101 formed in a first area of a substrate 150;
a plurality of first via structures 181, 183, 185 formed in a second area of the substrate, the second area being disposed next to the first area along a first lateral direction (left to right direction of the page);
a first one 166 of a plurality of frontside interconnect structures formed on a first side (lower side) of the substrate, wherein the first frontside interconnect structure is coupled to gate terminals of access transistors 111 of the plurality of first memory cells (Fig. 1(a) shows 113 is connected to the gate, [0009], [0037]; and
a first one 177 of a plurality of backside interconnect structures formed on a second side (upper side) of the substrate vertically opposite to the first side, wherein the first backside interconnect structure is coupled to the first frontside interconnect structure through one or more of the plurality of first via structures (as shown 166 and 177 are connected through vias 181, 183, 185).
Arslan shows the selector but does not explicitly talk about access transistor.
Liaw shows in Fig. 2, 4D wherein the first frontside interconnect structure is coupled to gate terminals 406 of access transistors AT-1 of the plurality of first memory cells 202
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Thus, it would have been obvious to one of ordinary skill in the art at the time the application was filed to realize the selector in Arslan works like an access transistor to access to the memory cells based on control signals wordlines (Liaw, [0023] – [0024]).
Regarding claim 2: Arslan teaches in Fig. 1(b) wherein the first frontside interconnect structure and the first backside interconnect structure both extend along the first lateral direction.
Regarding claims 3, 23: Arslan teaches in [0009] and Liaw teaches in Fig. 1 about memory array and therefore teaches about a plurality of second memory cells formed in the first area of the substrate;
a plurality of second via structures formed in the second area of the substrate;
a second one of the plurality of frontside interconnect structures coupled to gate terminals of access transistors of the plurality of second memory cells; and
a second one of the plurality of backside interconnect structures coupled to the second frontside interconnect structure through one or more of the plurality of second via structures;
wherein the second frontside interconnect structure and the second backside interconnect structure both extend along the first lateral direction.
It would have been obvious to one of ordinary skill in the art, at the time of applicant was filed , since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art.
St. Regis Paper Co. v. Bemis Co., 193 USPQ 8
Regarding claims 4, 16, 24: Arslan teaches in [0053] wherein each of the plurality of first memory cells and the plurality of second memory cells includes a static random access memory (SRAM) cell.
Regarding claim 5: Liaw teaches in Fig. 1 wherein the second memory cells are aligned with the first memory cells along a second lateral direction perpendicular to the first lateral direction, while the one or more first via structures are displaced from the one or more second via structures in both of the first and second lateral directions.
Regarding claims 6, 13: Arslan teaches in Fig. 1(b) wherein the one or more first via structures each extend through the substrate.
Regarding claim 7: As explained in claim 1, Arslan in view of Liaw teaches a second one of the plurality of frontside interconnect structures, wherein the second frontside interconnect structure is vertically disposed between the substrate and the first frontside interconnect structure; and
a second one of the plurality of backside interconnect structures, wherein the second backside interconnect structure is vertically disposed between the substrate and the first backside interconnect structure.
It would have been obvious to one of ordinary skill in the art, at the time of applicant was filed , since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art.
St. Regis Paper Co. v. Bemis Co., 193 USPQ 8
Regarding claim 8: As explained in claim 1, Arslan in view of Liaw teaches wherein the one or more first via structures are each in direct contact with the second frontside interconnect structure and the second backside interconnect structure.
It would have been obvious to one of ordinary skill in the art, at the time of applicant was filed , since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art.
St. Regis Paper Co. v. Bemis Co., 193 USPQ 8
Regarding claims 10, 22: Liaw teaches in Fig. 4A-4D wherein the first frontside interconnect structure and the first backside interconnect structure operatively serve as a portion of a word line of the first memory cells.
Regarding claims 11, 25: Liaw teaches in Fig. 1 wherein the first memory cells are configured to be arranged along a row and across a plurality of columns of a memory array, and wherein the memory array is formed in the first area.
Regarding claims 12, 17, 21: As explained above in claims 1-2, Arslan in view of Liaw teaches all the limitations.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitation allowable is “wherein the first interconnect structure, the second frontside interconnect structure, and the first backside interconnect structure each extend in the first lateral direction, while the second backside interconnect structure extends in a second lateral direction perpendicular to the first lateral direction”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
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/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
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