DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
This is a Non-Final office action base don application 18/803,363 filed August 13, 2024. Claims 1-19 are currently pending and have been considered below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for a patent.
Claim(s) 1-6, 11-12, & 15-16 is/are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Chiu (Pre-Grant Publication 2020/0365655).
Regarding claim 1, Chiu discloses a semiconductor device comprising:
forming insulation material (Fig. 1-11, 114) over a semiconductor substrate (Paragraph [0009]);
forming a first contact hole extending through the insulation material;
forming a first conductive contact (112) in the first contact hole;
forming a lower electrode layer (130) over the insulation material and electrically connected with the first conductive contact;
forming a resistive switching dielectric material layer (140) directly on the lower electrode layer;
forming an upper electrode layer (150) directly on the resistive switching dielectric material layer;
selectively removing portions of the upper electrode layer to form a block of the upper electrode layer (Fig. 4; 152);
selectively removing portions of the resistive switching dielectric material layer to form a block of the resistive switching dielectric material layer (142) disposed under the block of the upper electrode layer;
forming insulation spacers (Fig. 6, 180) on the lower electrode layer and extending along sidewalls of the block of the upper electrode layer and the block of the resistive switching dielectric material layer; and
selectively removing portions of the lower electrode layer to form a block of the lower electrode layer (Fig. 7, 132/134), wherein the block of the lower electrode layer is disposed under the insulation spacers and the block of the resistive switching dielectric material layer and the block of the upper electrode layer.
Regarding claim 2, Chiu further discloses:
the selectively removing portions of the upper electrode layer and the selectively removing portions of the resistive switching dielectric material layer comprise: forming photoresist (Fig. 3, PM) over the upper electrode layer and the resistive switching dielectric material layer; exposing and developing the photoresist to remove portions of the photoresist to form a block of the photoresist (172); and performing one or more etches to selectively remove portions of the upper electrode layer and portions of the resistive switching dielectric material layer, wherein the block of the upper electrode layer and the block of the resistive switching dielectric material layer are disposed under the block of the photoresist (Fig. 4, Paragraph [0018-0020]).
Regarding claim 3, Chiu further discloses:
the insulation spacers (180) include inner facing side surfaces that face each other, and outer facing side surfaces that face away from each other (Fig. 7);
the block of the upper electrode layer and the block of the resistive switching dielectric material layer include side surfaces that abut the inner facing side surfaces of the insulation spacers (Fig. 7); and
the block of the lower electrode layer includes side surfaces aligned with the outer facing side surfaces of the insulation spacers (Fig. 7).
Regarding claim 4, Chiu further discloses:
wherein before the selectively removing portions of the upper electrode layer and the selectively removing portions of the resistive switching dielectric material layer, comprising: forming a conductive layer (160) on the upper electrode layer (150); and
selectively removing portions of the conductive layer to form a block of the conductive layer (Fig. 4, 162);
wherein after the selectively removing portions of the upper electrode layer to form a block of the upper electrode layer (152), the block of the conductive layer is disposed on the block of the upper electrode layer.
Regarding claim 5, Chiu further discloses:
forming a transistor (Fig. 11, 912) on the semiconductor substrate; and
forming a second conductive contact such one of a metallization layer/ via interconnect (M1-M3/V1-V4) that is electrically connected to the transistor and to the first conductive contact (112/M4).
Regarding claim 6, Chiu further discloses:
the second conductive contact comprises a metal material (Paragraph [0035]).
Regarding claim 11, Chiu further discloses:
after the forming of the block of the lower electrode layer, thickening the insulation spacers by depositing spacer/dielectric layer (190) such that the insulation spacers extend along sidewalls of the block of the lower electrode layer (Fig. 8).
Regarding claim 12, Chiu further discloses:
the first conductive contact (112/M4) comprises a metal material (Paragraph [0035]).
Regarding claim 15, Chiu further discloses:
the lower electrode layer and the upper electrode layer each comprise TiN, TaN, HfN, TaAlN, Ti, Ta, Pt, Iridium, or Ruthenium (Paragraph [0012 & 0015]).
Regarding claim 16, Chiu further discloses:
the resistive switching dielectric material layer comprises HfO2, Al2O3, TaOx, TiOx, WOx, VOx or CuOx (Paragraph [0013]).
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 & 13 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Chiu (Pre-Grant Publication 2020/0365655) in view of Yang (Pre-Grant Publication 2019/0074440).
Regarding claim 7 & 13, Chiu disclose all of the limitations of claim 1 (addressed above). Chiu does not explicitly disclose the first and second conductive contact comprises copper or tungsten. However Yang disclose a semiconductor device comprising:
A first conductive contact (Fig. 2, 106) and a second conductive contact (240) wherein the first and second conductive contact can comprises a material such as copper or tungsten.
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first and second conductive contacts comprising a material such as copper or tungsten because copper or tungsten are well known conductive metal exhibiting high conductivity.
Claim 8-10 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Chiu (Pre-Grant Publication 2020/0365655) in view of Chu (Pre-Grant Publication 2025/03031923).
Regarding claim 8-10, Chiu disclose all of the limitations of claim 1 (addressed above). Chiu does not explicitly disclose forming a conductive layer on the insulation material and selectively removing portions of the conductive layer to form a block of the conductive layer. However Chu discloses a semiconductor device comprising:
forming a conductive layer (Fig. 3, 302) on a insulation material (218) wherein the conductive layer can comprise TaN (Paragraph [0035]); and
selectively removing portions of the conductive layer to form a block of the conductive layer that is disposed between the block of the lower electrode layer (306) and the first conductive contact (244)(Paragraph [0066]).
The block the conductive layer comprises sidewalls that are aligned with sidewalls of the block of the lower electrode layer (306) (Fig. 3).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the conductive layer comprising TaN between the lower electrode and first conductive contact because it will serve as a barrier layer that will resist migration of metal ions from diffusing between the conductive contact and lower electrode (Paragraph [0035]).
Claim 14 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Chiu (Pre-Grant Publication 2020/0365655) in view of Ando (Pre-Grant Publication 2021/0391536).
Regarding claim 14, Chiu disclose all of the limitations of claim 1 (addressed above). Chiu does not explicitly disclose the first conductive contact comprises a layer of TaN and Ta. However Ando disclose a semiconductor device comprising:
A first conductive contact (Fig. 13, 306) wherein the first conductive contact includes a layer (308) of TaN and Ta (Paragraph [0040]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first conductive layer including a layer comprising TaN and Ta between the layer will serve as a barrier metal layer that will prevent migration of metal ions from diffusing between the first conductive contact and an insulating dielectric (304) (Paragraph [0040]).
Claim 17-19 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Chiu (Pre-Grant Publication 2020/0365655) in view of Zhou (Pre-Grant Publication 2018/0145253).
Regarding claim 17-19, Chiu disclose all of the limitations of claim 1 (addressed above). Chiu does not explicitly disclose the resistive switching dielectric material comprises a sublayer of HfO2 and a sublayer of Al2O3, a sublayer of HfO2, a sublayer of Hf, and a sublayer of TaOx, a sublayer of HfO2, a sublayer of Ti, and a sublayer of TiOx. However Zhou discloses a semiconductor device comprising:
A resistive dielectric material (Fig. 3f, 42) wherein the resistive switching dielectric can be include sublayers such as a sublayer of HfO2 and a sublayer of Al2O3, a sublayer of HfO2, a sublayer of Hf, and a sublayer of TaOx, a sublayer of HfO2, a sublayer of Ti, and a sublayer of TiOx (Paragraph [0021]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the resistive switching layer to include sublayer of different materials to vary the performance and stability of the RRAM based on the material (Paragraph [0006]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Trinh (Pre-Grant Publication 2025/0228146) discloses a RRAM memory structure wherein the resistive switching layer includes a dual resistive switching layer.
Chen (Pre-Grant Publication 2025/0133969) discloses a resistive memory with a top electrode with reduced corner erosion.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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