DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(e) the invention was described in (1) an application for patent, published under section 122(b), by another filed in the United States before the invention by the applicant for patent or (2) a patent granted on an application for patent by another filed in the United States before the invention by the applicant for patent, except that an international application filed under the treaty defined in section 351(a) shall have the effects for purposes of this subsection of an application filed in the United States only if the international application designated the United States and was published under Article 21(2) of such treaty in the English language.
Claim(s) 1-16 are rejected under pre-AIA 35 U.S.C. 102(e) as being anticipated by Yamazaki 207 (U.S. PGPub 2011/0090207).
The applied reference has common inventors with the instant application. Based upon the pre-AIA 35 U.S.C. 102(e) date of the reference, it constitutes prior art. This rejection under pre-AIA 35 U.S.C. 102(e) might be overcome either by a showing under 37 CFR 1.132 that any invention disclosed but not claimed in the reference was derived from the inventor or joint inventors (i.e., the inventive entity) of this application and is thus not the invention “by another,” or if the same invention is not being claimed, by an appropriate showing under 37 CFR 1.131(a).
Regarding claims 1-6, Yamazaki 207 teaches a first insulating layer; a first conductive layer over the first insulating layer; an oxide semiconductor layer comprising a channel formation region, a region in contact with a side surface of the first conductive layer, and a region in contact with a top surface of the first conductive layer; a second conductive layer comprising a region over the oxide semiconductor layer and a region configured to serve as a wiring layer; a second insulating layer over the oxide semiconductor layer; and a third conductive layer over the second insulating layer, wherein the first conductive layer is a single layer comprising molybdenum, wherein the oxide semiconductor layer comprises indium, gallium, and zinc, wherein the second conductive layer is a stacked layer comprising a first titanium film, a first aluminum film over the first titanium film, and a second titanium film over the first aluminum film, wherein the third conductive layer is a stacked layer comprising a third titanium film and a second aluminum film, wherein an end portion of the first conductive layer comprises a tapered shape, wherein the first insulating layer comprises a first region, a second region, and a third region between the first region and the second region, wherein the first region and the second region of the first insulating layer is in contact with a bottom surface of the oxide semiconductor layer, wherein the third region of the first insulating layer is in contact with a bottom surface of the first conductive layer, wherein the second conductive layer and the first conductive layer overlap each other, wherein the second conductive layer and the oxide semiconductor layer overlap each other, and wherein the second conductive layer and the second insulating layer overlap each other;
a third insulating layer over the second conductive layer;
wherein the oxide semiconductor layer comprises a microcrystalline portion;
wherein a grain diameter of the microcrystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm;
wherein the first conductive layer is configured to serve as a source electrode or a drain electrode,
wherein the second insulating layer is configured to serve as a gate insulating layer, and
wherein the third conductive layer is configure to serve as a gate electrode;
(Figs. 7A-7B, element numbers are the same as application Figs. 5A-5B; [0206]-[0250]; [0165]).
Regarding claims 7-11, Yamazaki 207 teaches a semiconductor device comprising:
a first insulating layer; a first conductive layer over the first insulating layer; an oxide semiconductor layer comprising a channel formation region, a region in contact with a side surface of the first conductive layer, and a region in contact with a top surface of the first conductive layer;
a second conductive layer comprising a region over the oxide semiconductor layer and a region configured to serve as a wiring layer; a second insulating layer over the oxide semiconductor layer; and
a third conductive layer over the second insulating layer, wherein the first conductive layer is a single layer comprising molybdenum, wherein the oxide semiconductor layer comprises indium, gallium, and zinc, wherein the second conductive layer is a stacked layer comprising a first titanium film, a first aluminum film over the first titanium film, and a second titanium film over the first aluminum film,
wherein the third conductive layer is a stacked layer comprising a third titanium film and a second aluminum film, wherein an end portion of the first conductive layer comprises a tapered shape, wherein the first insulating layer comprises a first region, a second region, and a third region between the first region and the second region in a cross-sectional view in a channel length direction, wherein the first region and the second region of the first insulating layer is in contact with a bottom surface of the oxide semiconductor layer, wherein the third region of the first insulating layer is in contact with a bottom surface of the first conductive layer, wherein the second conductive layer and the first conductive layer overlap each other, wherein the second conductive layer and the oxide semiconductor layer overlap each other, and wherein the second conductive layer and the second insulating layer overlap each other;
a third insulating layer over the second conductive layer;
wherein the oxide semiconductor layer comprises a microcrystalline portion;
wherein a grain diameter of the microcrystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm;
wherein the first conductive layer is configured to serve as a source electrode or a drain electrode;
the second insulating layer is configured to serve as a gate insulating layer, and
wherein the third conductive layer is configured to serve as a gate electrode
(Figs. 7A-7B, element numbers are the same as application Figs. 5A-5B; [0206]-[0250]; [0165]).
Regarding claims 12-16, Yamazaki 207 teaches a semiconductor device comprising:
a first insulating layer; a first conductive layer over the first insulating layer; an oxide semiconductor layer comprising a channel formation region, a region in contact with a side surface of the first conductive layer, and a region in contact with a top surface of the first conductive layer; a second conductive layer comprising a region over the oxide semiconductor layer and a region configured to serve as a wiring layer; a second insulating layer over the oxide semiconductor layer; and
a third conductive layer over the second insulating layer, wherein the first conductive layer is a single layer comprising molybdenum, wherein the oxide semiconductor layer comprises indium,
wherein the second conductive layer is a stacked layer comprising a first titanium film, a first aluminum film over the first titanium film, and a second titanium film over the first aluminum film, wherein the third conductive layer is a stacked layer comprising a third titanium film and a second aluminum film,
wherein an end portion of the first conductive layer comprises a tapered shape, wherein the first insulating layer comprises a first region, a second region, and a third region between the first region and the second region in a cross-sectional view in a channel length direction, wherein the first region and the second region of the first insulating layer is in contact with a bottom surface of the oxide semiconductor layer, wherein the third region of the first insulating layer is in contact with a bottom surface of the first conductive layer, wherein the second conductive layer and the first conductive layer overlap each other, wherein the second conductive layer and the oxide semiconductor layer overlap each other, and wherein the second conductive layer and the second insulating layer overlap each other;
a third insulating layer over the second conductive layer;
wherein the oxide semiconductor layer comprises a microcrystalline portion;
wherein a grain diameter of the microcrystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm;
wherein the first conductive layer is configured to serve as a source electrode or a drain electrode,
wherein the second insulating layer is configured to serve as a gate insulating layer, and
wherein the third conductive layer is configured to serve as a gate electrode
(Figs. 7A-7B, element numbers are the same as application Figs. 5A-5B; [0206]-[0250]; [0165]).
Claim(s) 1-16 are rejected under pre-AIA 35 U.S.C. 102(e) as being anticipated by Yamazaki 204 (U.S. PGPub 2011/0090204).
The applied reference has common inventors with the instant application. Based upon the pre-AIA 35 U.S.C. 102(e) date of the reference, it constitutes prior art. This rejection under pre-AIA 35 U.S.C. 102(e) might be overcome either by a showing under 37 CFR 1.132 that any invention disclosed but not claimed in the reference was derived from the inventor or joint inventors (i.e., the inventive entity) of this application and is thus not the invention “by another,” or if the same invention is not being claimed, by an appropriate showing under 37 CFR 1.131(a).
Regarding claims 1-6, Yamazaki 204 teaches a first insulating layer; a first conductive layer over the first insulating layer; an oxide semiconductor layer comprising a channel formation region, a region in contact with a side surface of the first conductive layer, and a region in contact with a top surface of the first conductive layer; a second conductive layer comprising a region over the oxide semiconductor layer and a region configured to serve as a wiring layer; a second insulating layer over the oxide semiconductor layer; and a third conductive layer over the second insulating layer, wherein the first conductive layer is a single layer comprising molybdenum, wherein the oxide semiconductor layer comprises indium, gallium, and zinc, wherein the second conductive layer is a stacked layer comprising a first titanium film, a first aluminum film over the first titanium film, and a second titanium film over the first aluminum film, wherein the third conductive layer is a stacked layer comprising a third titanium film and a second aluminum film, wherein an end portion of the first conductive layer comprises a tapered shape, wherein the first insulating layer comprises a first region, a second region, and a third region between the first region and the second region, wherein the first region and the second region of the first insulating layer is in contact with a bottom surface of the oxide semiconductor layer, wherein the third region of the first insulating layer is in contact with a bottom surface of the first conductive layer, wherein the second conductive layer and the first conductive layer overlap each other, wherein the second conductive layer and the oxide semiconductor layer overlap each other, and wherein the second conductive layer and the second insulating layer overlap each other;
a third insulating layer over the second conductive layer;
wherein the oxide semiconductor layer comprises a microcrystalline portion;
wherein a grain diameter of the microcrystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm;
wherein the first conductive layer is configured to serve as a source electrode or a drain electrode,
wherein the second insulating layer is configured to serve as a gate insulating layer, and
wherein the third conductive layer is configured to serve as a gate electrode;
(Figs. 7A-7B, element numbers are the same as application Figs. 5A-5B; [0200]-[0250]; [0172]).
Regarding claims 7-11, Yamazaki 204 teaches a semiconductor device comprising:
a first insulating layer; a first conductive layer over the first insulating layer; an oxide semiconductor layer comprising a channel formation region, a region in contact with a side surface of the first conductive layer, and a region in contact with a top surface of the first conductive layer;
a second conductive layer comprising a region over the oxide semiconductor layer and a region configured to serve as a wiring layer; a second insulating layer over the oxide semiconductor layer; and
a third conductive layer over the second insulating layer, wherein the first conductive layer is a single layer comprising molybdenum, wherein the oxide semiconductor layer comprises indium, gallium, and zinc, wherein the second conductive layer is a stacked layer comprising a first titanium film, a first aluminum film over the first titanium film, and a second titanium film over the first aluminum film,
wherein the third conductive layer is a stacked layer comprising a third titanium film and a second aluminum film, wherein an end portion of the first conductive layer comprises a tapered shape, wherein the first insulating layer comprises a first region, a second region, and a third region between the first region and the second region in a cross-sectional view in a channel length direction, wherein the first region and the second region of the first insulating layer is in contact with a bottom surface of the oxide semiconductor layer, wherein the third region of the first insulating layer is in contact with a bottom surface of the first conductive layer, wherein the second conductive layer and the first conductive layer overlap each other, wherein the second conductive layer and the oxide semiconductor layer overlap each other, and wherein the second conductive layer and the second insulating layer overlap each other;
a third insulating layer over the second conductive layer;
wherein the oxide semiconductor layer comprises a microcrystalline portion;
wherein a grain diameter of the microcrystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm;
wherein the first conductive layer is configured to serve as a source electrode or a drain electrode;
the second insulating layer is configured to serve as a gate insulating layer, and
wherein the third conductive layer is configure to serve as a gate electrode
(Figs. 7A-7B, element numbers are the same as application Figs. 5A-5B; [0200]-[0250]; [0172]).
Regarding claims 12-16, Yamazaki 204 teaches a semiconductor device comprising:
a first insulating layer; a first conductive layer over the first insulating layer; an oxide semiconductor layer comprising a channel formation region, a region in contact with a side surface of the first conductive layer, and a region in contact with a top surface of the first conductive layer; a second conductive layer comprising a region over the oxide semiconductor layer and a region configured to serve as a wiring layer; a second insulating layer over the oxide semiconductor layer; and
a third conductive layer over the second insulating layer, wherein the first conductive layer is a single layer comprising molybdenum, wherein the oxide semiconductor layer comprises indium,
wherein the second conductive layer is a stacked layer comprising a first titanium film, a first aluminum film over the first titanium film, and a second titanium film over the first aluminum film, wherein the third conductive layer is a stacked layer comprising a third titanium film and a second aluminum film,
wherein an end portion of the first conductive layer comprises a tapered shape, wherein the first insulating layer comprises a first region, a second region, and a third region between the first region and the second region in a cross-sectional view in a channel length direction, wherein the first region and the second region of the first insulating layer is in contact with a bottom surface of the oxide semiconductor layer, wherein the third region of the first insulating layer is in contact with a bottom surface of the first conductive layer, wherein the second conductive layer and the first conductive layer overlap each other, wherein the second conductive layer and the oxide semiconductor layer overlap each other, and wherein the second conductive layer and the second insulating layer overlap each other;
a third insulating layer over the second conductive layer;
wherein the oxide semiconductor layer comprises a microcrystalline portion;
wherein a grain diameter of the microcrystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm;
wherein the first conductive layer is configured to serve as a source electrode or a drain electrode,
wherein the second insulating layer is configured to serve as a gate insulating layer, and
wherein the third conductive layer is configured to serve as a gate electrode
(Figs. 7A-7B, element numbers are the same as application Figs. 5A-5B; [0200]-[0250]; [0172]).
Claim(s) 1-16 are rejected under pre-AIA 35 U.S.C. 102(e) as being anticipated by Yamazaki 183 (U.S. PGPub 2011/0090183).
The applied reference has common inventors with the instant application. Based upon the pre-AIA 35 U.S.C. 102(e) date of the reference, it constitutes prior art. This rejection under pre-AIA 35 U.S.C. 102(e) might be overcome either by a showing under 37 CFR 1.132 that any invention disclosed but not claimed in the reference was derived from the inventor or joint inventors (i.e., the inventive entity) of this application and is thus not the invention “by another,” or if the same invention is not being claimed, by an appropriate showing under 37 CFR 1.131(a).
Regarding claims 1-6, Yamazaki 183 teaches a first insulating layer; a first conductive layer over the first insulating layer; an oxide semiconductor layer comprising a channel formation region, a region in contact with a side surface of the first conductive layer, and a region in contact with a top surface of the first conductive layer; a second conductive layer comprising a region over the oxide semiconductor layer and a region configured to serve as a wiring layer; a second insulating layer over the oxide semiconductor layer; and a third conductive layer over the second insulating layer, wherein the first conductive layer is a single layer comprising molybdenum, wherein the oxide semiconductor layer comprises indium, gallium, and zinc, wherein the second conductive layer is a stacked layer comprising a first titanium film, a first aluminum film over the first titanium film, and a second titanium film over the first aluminum film, wherein the third conductive layer is a stacked layer comprising a third titanium film and a second aluminum film, wherein an end portion of the first conductive layer comprises a tapered shape, wherein the first insulating layer comprises a first region, a second region, and a third region between the first region and the second region, wherein the first region and the second region of the first insulating layer is in contact with a bottom surface of the oxide semiconductor layer, wherein the third region of the first insulating layer is in contact with a bottom surface of the first conductive layer, wherein the second conductive layer and the first conductive layer overlap each other, wherein the second conductive layer and the oxide semiconductor layer overlap each other, and wherein the second conductive layer and the second insulating layer overlap each other;
a third insulating layer over the second conductive layer;
wherein the oxide semiconductor layer comprises a microcrystalline portion;
wherein a grain diameter of the microcrystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm;
wherein the first conductive layer is configured to serve as a source electrode or a drain electrode,
wherein the second insulating layer is configured to serve as a gate insulating layer, and
wherein the third conductive layer is configured to serve as a gate electrode;
(Figs. 7A-7B, element numbers are the same as application Figs. 5A-5B; [0157]-[0200]; [0131]).
Regarding claims 7-11, Yamazaki 183 teaches a semiconductor device comprising:
a first insulating layer; a first conductive layer over the first insulating layer; an oxide semiconductor layer comprising a channel formation region, a region in contact with a side surface of the first conductive layer, and a region in contact with a top surface of the first conductive layer;
a second conductive layer comprising a region over the oxide semiconductor layer and a region configured to serve as a wiring layer; a second insulating layer over the oxide semiconductor layer; and
a third conductive layer over the second insulating layer, wherein the first conductive layer is a single layer comprising molybdenum, wherein the oxide semiconductor layer comprises indium, gallium, and zinc, wherein the second conductive layer is a stacked layer comprising a first titanium film, a first aluminum film over the first titanium film, and a second titanium film over the first aluminum film,
wherein the third conductive layer is a stacked layer comprising a third titanium film and a second aluminum film, wherein an end portion of the first conductive layer comprises a tapered shape, wherein the first insulating layer comprises a first region, a second region, and a third region between the first region and the second region in a cross-sectional view in a channel length direction, wherein the first region and the second region of the first insulating layer is in contact with a bottom surface of the oxide semiconductor layer, wherein the third region of the first insulating layer is in contact with a bottom surface of the first conductive layer, wherein the second conductive layer and the first conductive layer overlap each other, wherein the second conductive layer and the oxide semiconductor layer overlap each other, and wherein the second conductive layer and the second insulating layer overlap each other;
a third insulating layer over the second conductive layer;
wherein the oxide semiconductor layer comprises a microcrystalline portion;
wherein a grain diameter of the microcrystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm;
wherein the first conductive layer is configured to serve as a source electrode or a drain electrode;
the second insulating layer is configured to serve as a gate insulating layer, and
wherein the third conductive layer is configured to serve as a gate electrode
(Figs. 7A-7B, element numbers are the same as application Figs. 5A-5B; [0157]-[0200]; [0131]).
Regarding claims 12-16, Yamazaki 183 teaches a semiconductor device comprising:
a first insulating layer; a first conductive layer over the first insulating layer; an oxide semiconductor layer comprising a channel formation region, a region in contact with a side surface of the first conductive layer, and a region in contact with a top surface of the first conductive layer; a second conductive layer comprising a region over the oxide semiconductor layer and a region configured to serve as a wiring layer; a second insulating layer over the oxide semiconductor layer; and
a third conductive layer over the second insulating layer, wherein the first conductive layer is a single layer comprising molybdenum, wherein the oxide semiconductor layer comprises indium,
wherein the second conductive layer is a stacked layer comprising a first titanium film, a first aluminum film over the first titanium film, and a second titanium film over the first aluminum film, wherein the third conductive layer is a stacked layer comprising a third titanium film and a second aluminum film,
wherein an end portion of the first conductive layer comprises a tapered shape, wherein the first insulating layer comprises a first region, a second region, and a third region between the first region and the second region in a cross-sectional view in a channel length direction, wherein the first region and the second region of the first insulating layer is in contact with a bottom surface of the oxide semiconductor layer, wherein the third region of the first insulating layer is in contact with a bottom surface of the first conductive layer, wherein the second conductive layer and the first conductive layer overlap each other, wherein the second conductive layer and the oxide semiconductor layer overlap each other, and wherein the second conductive layer and the second insulating layer overlap each other;
a third insulating layer over the second conductive layer;
wherein the oxide semiconductor layer comprises a microcrystalline portion;
wherein a grain diameter of the microcrystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm;
wherein the first conductive layer is configured to serve as a source electrode or a drain electrode,
wherein the second insulating layer is configured to serve as a gate insulating layer, and
wherein the third conductive layer is configured to serve as a gate electrode
(Figs. 7A-7B, element numbers are the same as application Figs. 5A-5B; [0157]-[0200]; [0131]).
Conclusion
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/ALIA SABUR/ Primary Examiner, Art Unit 2812
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