DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein a top surface of the air gap structure is coplanar with a top surface of the buried conductive layer”, as recited in claim 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (U.S. 2014/0254239 A1, hereinafter refer to Song) in view of Wei et al. (U.S. 2022/0216210 A1, hereinafter refer to Wei).
Regarding Claim 1: Song discloses a method for fabricating a semiconductor device (see Song, Fig.3 as shown below and ¶ [0002]), comprising:
PNG
media_image1.png
309
557
media_image1.png
Greyscale
providing a substrate and forming an isolation layer (102) in the substrate to define a plurality of active areas (103) (see Song, Fig.3 as shown above);
forming an opening (109) in the substrate (see Song, Fig.3 as shown above);
conformally forming a layer of spacer material (116) in the opening (109) (see Song, Fig.3 as shown above);
performing a spacer etching process to remove a portion of the spacer material (116) and form an in-recess spacer (116) in the opening (109) (see Song, Fig.3 as shown above); and
forming a buried conductive layer (115/114) in the opening (109) and covering the in-recess spacer (116) (see Song, Fig.3 as shown above and ¶ [0046]).
Song is silent upon explicitly disclosing wherein an air gap structure is formed in the isolation layer.
For support see Wei, which teaches wherein an air gap structure (117) is formed in the isolation layer (104) (see Wei, Fig.9 and ¶ [0038]).
PNG
media_image2.png
470
763
media_image2.png
Greyscale
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Song and Wei to enable an air gap structure to be formed in the isolation layer as taught by Wei in order to decrease the parasitic capacitance between the bit lines (and/or the bit line contact structures) and the capacitive contact structure.
Regarding Claim 2: Song as modified teaches a method for fabricating a semiconductor device as set forth in claim 1 as above. The combination of Song and Wei further teaches wherein the spacer material (Fig.3,116/Figs.6B-6E, 60) comprises silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbon silicon nitride (see Song, Fig.3 as shown above, Figs.6B-6E, and ¶ [0091]).
Regarding Claim 3: Song as modified teaches a method for fabricating a semiconductor device as set forth in claim 2 as above. The combination of Song and Wei further teaches wherein the buried conductive layer (114/115) comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, or a combination thereof (see Song, Fig.3 as shown above, ¶ [0045]- ¶ [0046], and ¶ [0053]).
Regarding Claim 5: Song as modified teaches a method for fabricating a semiconductor device as set forth in claim 1 as above. The combination of Song and Wei is silent upon explicitly disclosing wherein a ratio of a width of the bottom surface of the bottom portion to a width of the top surface of the top portion is between about 0.5 and about 0.95; a ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion is between about 0.025 and about 0.25; and a ratio of a height of the in-recess spacer to a height of the buried conductive layer is between about 0.5 and about 0.85.
However, the combination of Song and Wei teaches wherein a ratio of a width of the bottom surface of the bottom portion to a width of the top surface of the top portion is CD2/CD1; a ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion; and a ratio of a height of the in-recess spacer (116) to a height of the buried conductive layer (115) (see Song, Fig.3 as shown above).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the ratio of a width of the bottom surface of the bottom portion to a width of the top surface of the top portion and for the ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion; and for the ratio of a height of the in-recess spacer to a height of the buried conductive layer through routine experimentation and optimization to obtain optimal or desired device performance because the ratio of a width of the bottom surface of the bottom portion to a width of the top surface of the top portion and for the ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion; and for the ratio of a height of the in-recess spacer to a height of the buried conductive layer is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 6: Song as modified teaches a method for fabricating a semiconductor device as set forth in claim 1 as above. The combination of Song and Wei is silent upon explicitly disclosing wherein the in-recess spacer has a square ring-shaped cross-sectional profile from a top-view perspective.
However, since in-recess spacer 116 surrounds the opining 110, it necessary results ring-shaped cross-sectional profile from a top-view perspective (see Song, Fig.3 as shown above).
Hence, the configuration of the claimed in-recess spacer was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed in-recess spacer was significant.
Regarding Claim 7: Song as modified teaches a method for fabricating a semiconductor device as set forth in claim 1 as above. The combination of Song and Wei is silent upon explicitly disclosing wherein the buried conductive layer has a square cross-sectional profile from a top-view perspective.
However, Wei teaches conductive layer (130) has a square cross-sectional profile from a top-view perspective (see Wei, Figs.1 and 9).
Hence, the configuration of the claimed buried conductive layer was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive layer was significant.
Regarding Claim 8: Song as modified teaches a method for fabricating a semiconductor device as set forth in claim 7 as above. The combination of Song and Wei further teaches wherein the in-recess spacer (Fig.3,116/Figs.6B-6E, 60) comprises silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbon silicon nitride (see Song, Fig.3 as shown above, Figs.6B-6E, and ¶ [0091]).
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (U.S. 2014/0254239 A1, hereinafter refer to Song) and Wei et al. (U.S. 2022/0216210 A1, hereinafter refer to Wei) as applied to claim 3 above, and further in view of Dakshina-Murthy et al. (U.S. 2006/0094205 A1, hereinafter refer to Dakshina-Murthy).
Regarding Claim 4: Song as modified teaches a method for fabricating a semiconductor device as applied to claim 3 above. The combination of Song and Wei is silent upon explicitly disclosing wherein the spacer etching process is an anisotropic etching process.
For support see Dakshina-Murthy, which teaches wherein the spacer (60/32) etching process is an anisotropic etching process (see Dakshina-Murthy, Figs.7-8 and ¶ [0021]- ¶ [0022]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Song, Wei, and Dakshina-Murthy to enable the known anisotropic etching process for recessing the Song spacer according to the teachings of Dakshina-Murthy because one of ordinary skill in the art at the time of the invention would have been motivated to look to alternative suitable methods of performing the disclosed in-recess spacer and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (U.S. 2014/0254239 A1, hereinafter refer to Song) and Wei et al. (U.S. 2022/0216210 A1, hereinafter refer to Wei) as applied to claim 1 above, and further in view of Singh et al. (U.S. 2019/0385892 A1, hereinafter refer to Singh).
Regarding Claim 9: Song as modified teaches a method for fabricating a semiconductor device as applied to claim 1 above. The combination of Song and Wei is silent upon explicitly disclosing wherein the air gap structure includes an air gap enclosed by a liner.
For support see Rueger, which teaches wherein the air gap structure (130) includes an air gap enclosed by a liner (310) (see Singh, Fig.21 and ¶ [0013]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Song, Wei, and Singh to enable the combination of Song's and Wei's air gap structure to include an air gap enclosed by a liner as taught by Singh in order to improve isolation properties between devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BITEW A DINKE/Primary Examiner, Art Unit 2812
Prosecution Insights