DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(e) the invention was described in (1) an application for patent, published under section 122(b), by another filed in the United States before the invention by the applicant for patent or (2) a patent granted on an application for patent by another filed in the United States before the invention by the applicant for patent, except that an international application filed under the treaty defined in section 351(a) shall have the effects for purposes of this subsection of an application filed in the United States only if the international application designated the United States and was published under Article 21(2) of such treaty in the English language.
Claims 2-4 and 8-10 are rejected under pre-AIA 35 U.S.C. 102(e) as being anticipated by Park (US Pub. No. 2008/0258141).
Regarding claim 2, in FIGs. 10 and 1-2, Park discloses a display device comprising: a pixel, the pixel comprising: a first transistor (12 in FIGs. 1-2; FIG. 10); and a capacitor (14, paragraphs [0036], [0072], claim 36), wherein the display device comprises: a first conductive film (42, paragraph [0048]) over a first substrate (40, paragraph [0048]); a first insulating film (44, paragraph [0048]) over the first conductive film; a first semiconductor film (46, paragraph [0048]) over the first insulating film; a second semiconductor film (52a, paragraph [0048]) over the first semiconductor film; a third semiconductor film (52b, paragraph [0048]) over the first semiconductor film; a second conductive film (54a, paragraph [0050]) over the second semiconductor film; a third conductive film (54b, paragraph [0050]) over the third semiconductor film; and a second insulating film (48, paragraph [0048]) over (or overlapping) the second conductive film and the third conductive film, wherein the first conductive film comprises a region configured to function as a gate electrode of the first transistor, wherein the first semiconductor film comprises a channel formation region of the first transistor, wherein the second conductive film comprises a region configured to function as one of a source electrode and a drain electrode of the first transistor, wherein the second conductive film comprises a region configured to function as one electrode of the capacitor (see FIG. 1), wherein the third conductive film comprises a region configured to function as the other of the source electrode and the drain electrode of the first transistor, wherein the second insulating film is provided over (or overlapping) the second semiconductor film and the third semiconductor film, wherein, in a cross-sectional view in a channel length direction of the first transistor, the second semiconductor film comprises a region protruding towards the channel formation region of the first transistor from an end portion of the second conductive film, wherein, in the cross-sectional view in the channel length direction of the first transistor, the third semiconductor film comprises a region protruding towards the channel formation region of the first transistor from an end portion of the third conductive film (e.g. the corners/edges of 52a/b facing toward channel formation region), wherein the second conductive film comprises a region in contact with a top surface of the first insulating film and a region in contact with a side surface of the second semiconductor film, and wherein the third conductive film comprises a region in contact with the top surface of the first insulating film and a region in contact with a side surface of the third semiconductor film (e.g. the outer portions of 54a/b).
Regarding claim 3, in FIGs. 10 and 1-2, Park discloses a display device comprising: a pixel, the pixel comprising: a first transistor (12 in FIGs. 1-2; FIG. 10); and a capacitor (14, paragraphs [0036], [0072], claim 36), wherein the display device comprises: a first conductive film (42, paragraph [0048]) over a first substrate; a first insulating film (44) over the first conductive film; a first semiconductor film (46) over the first insulating film; a second semiconductor film (52a) over and in contact with the first semiconductor film; a third semiconductor film (52b) over and in contact with the first semiconductor film; a second conductive film (54a) over and in contact with the second semiconductor film; a third conductive film (54b) over and in contact with the third semiconductor film; and a second insulating film (48) over (or overlapping) the second conductive film and the third conductive film, wherein the first conductive film comprises a region configured to function as a gate electrode of the first transistor, wherein the first semiconductor film comprises a channel formation region of the first transistor, wherein the second conductive film comprises a region configured to function as one of a source electrode and a drain electrode of the first transistor, wherein the second conductive film comprises a region configured to function as one electrode of the capacitor (see FIG. 1), wherein the third conductive film comprises a region configured to function as the other of the source electrode and the drain electrode of the first transistor, wherein the second insulating film is in contact with a top surface of the second semiconductor film and a top surface of the third semiconductor film (48 contacts a top surface of both 52a and 52b), wherein, in a cross-sectional view in a channel length direction of the first transistor, the second semiconductor film comprises a region protruding towards the channel formation region of the first transistor from an end portion of the second conductive film, wherein, in the cross-sectional view in the channel length direction of the first transistor, the third semiconductor film comprises a region protruding towards the channel formation region of the first transistor from an end portion of the third conductive film (e.g. the corners/edges of 52a/b facing toward channel formation region), wherein the second conductive film comprises a region in contact with a top surface of the first insulating film and a region in contact with a side surface of the second semiconductor film, and wherein the third conductive film comprises a region in contact with the top surface of the first insulating film and a region in contact with a side surface of the third semiconductor film.
Regarding claim 4, in FIGs. 10 and 1-2, Park discloses a display device comprising: a pixel, the pixel comprising: a first transistor (12 in FIGs. 1-2; FIG. 10); and a capacitor (14, paragraphs [0036], [0072], claim 36), wherein the display device comprises: a first conductive film (42, paragraph [0048]) over a first substrate; a first insulating film (44) over the first conductive film; a first semiconductor film (46) over the first insulating film; a second semiconductor film (52a) over and in contact with the first semiconductor film; a third semiconductor film (52b) over and in contact with the first semiconductor film; a second conductive film (54a) over and in contact with the second semiconductor film; a third conductive film (54b) over and in contact with the third semiconductor film; and a second insulating film (48) over (or overlapping) the second conductive film and the third conductive film, wherein the first conductive film comprises a region configured to function as a gate electrode of the first transistor, wherein the first semiconductor film comprises a channel formation region of the first transistor, wherein the second conductive film comprises a region configured to function as one of a source electrode and a drain electrode of the first transistor, wherein the second conductive film comprises a region configured to function as one electrode of the capacitor (see FIG. 1), wherein the third conductive film comprises a region configured to function as the other of the source electrode and the drain electrode of the first transistor, wherein the second insulating film is in contact with a top surface of the second semiconductor film and a top surface of the third semiconductor film (48 contacts a top surface of both 52a and 52b), wherein, in a cross-sectional view in a channel length direction of the first transistor, the second semiconductor film comprises a region protruding towards the channel formation region of the first transistor from an end portion of the second conductive film, wherein, in the cross-sectional view in the channel length direction of the first transistor, the third semiconductor film comprises a region protruding towards the channel formation region of the first transistor from an end portion of the third conductive film (e.g. the corners/edges of 52a/b facing toward channel formation region), wherein the second conductive film comprises a region in contact with a top surface of the first insulating film and a region in contact with a side surface of the second semiconductor film, and wherein the third conductive film comprises a region in contact with the top surface of the first insulating film and a region in contact with a side surface of the third semiconductor film, wherein a thickness (measured normal to the substrate top surface) of a region of the first semiconductor film overlapping with the second semiconductor film (vertical portion of 46) is larger than a thickness of a region of the first semiconductor film comprising the channel formation region (region of 46 overlapping with 42), and wherein a thickness of a region of the first semiconductor film overlapping with the third semiconductor film (vertical portion of 46) is larger than the thickness of the region of the first semiconductor film comprising the channel formation region (region of 46 overlapping with 42).
Regarding claims 8-10, in FIGs. 10 and 1-2, Park discloses that a carrier concentration of the second semiconductor film is higher than a carrier concentration of the first semiconductor film, and wherein a carrier concentration of the third semiconductor film is higher than the carrier concentration of the first semiconductor film (paragraph [0048]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Park (US Pub. No. 2008/0258141) in view of Mardilovich (US Pub. No. 2006/0060857).
Regarding claims 5-7, Park appears not to explicitly disclose that the gate electrode of the first transistor comprises copper.
The art however well recognized copper to be suitable for use as a gate electrode in a metal oxide transistor. See, for example, Mardilovich, paragraph [0012].
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious to a person of ordinary skill in the art at the time of invention to have formed the Park disclosed gate electrode to comprise copper for its recognized suitability as a gate electrode in a metal oxide transistor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUCKER J WRIGHT/Primary Examiner, Art Unit 2891
Prosecution Insights