DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 9-12, 18, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by He, US 10790005 B1.
As to claim 1, He discloses a memory device (see Fig 1), comprising:
an array of storage cells (see Fig 1 Ref 105), each storage cell coupled to one of multiple bitlines (see Fig 1 Ref 115) and one of multiple local wordlines (see Fig 1 Ref 110), and wherein
groups of the multiple local wordlines (see Col 7 Lines 39-51) are activated by master wordlines (see Fig 1 Ref XADD); and a wordline decoder (see Fig 1 Refs 120 and 165) to receive wordline address information (see Fig 1 Ref AREF) and to selectively activate an addressed wordline (see Fig 1 Ref RXADD) corresponding to the wordline address information,
the wordline decoder comprising gating circuitry operative during a first mode of operation (see Fig 6 Ref 610 and Col 18 Lines 37-45) to selectively suppress activation of the addressed wordline (see Fig 7 Ref SKIP) during a refresh operation (see Fig 7 Ref 720) during a current refresh period (see Fig 7 Ref N+2) based on a timing of an activate command associated with the addressed wordline (see Fig 6 Ref ACT).
As to claim 2, He discloses the memory device of claim 1, wherein:
the gating circuitry is to selectively suppress activation of the addressed wordline based on whether the addressed wordline was activated by a prior activate command within an immediately preceding refresh period (see Col 19 Lines 16-28).
As to claim 9, He discloses the memory device of claim 1, further comprising: register storage to store a mode value of a first state that represents operation in the first mode of operation (see Col 8 Lines 35-48), or to store a mode value of a second state that represents operation in a second mode of operation that at least partially disables the gating circuitry for at least a portion of the array of storage cells.
As to claim 10, He discloses the memory device of claim 9, wherein:
a setting of the mode value is based on a density of activate commands associated with portions of the array of storage cells (see Col 8 Lines 49-59).
As to claim 11, He discloses the memory device of claim 1, wherein:
the array of storage cells comprises an array of dynamic random access memory (DRAM) storage cells (see Col 10 Lines 14-24).
As to claim 12, He discloses a dynamic random access memory (DRAM) (see Col 10 Lines 14-24) integrated circuit (IC) memory chip (see Col 1 Lines 21-32), comprising:
an array of storage cells (see Fig 1 Ref 105), each storage cell coupled to one of multiple bitlines (see Fig 1 Ref 115) and one of multiple local wordlines (see Fig 1 Ref 110), and wherein
groups of the multiple local wordlines are activated by master wordlines (see Fig 1 Ref XADD); a wordline decoder (see Fig 1 Refs 120 and 165) to receive wordline address information (see Fig 1 Ref AREF) and to selectively activate an addressed wordline corresponding to the wordline address information (see Fig 1 Ref RXADD),
the wordline decoder comprising gating circuitry (see Fig 2) to selectively suppress activation of the addressed wordline (see Fig 7 Ref SKIP) during a refresh operation (see Fig 7 Ref 720) during a current refresh period (see Fig 7 Ref N+2) based on a timing of an activate command associated with the addressed wordline (see Fig 6 Ref ACT); and
register storage to store a mode value of a first state that enables the gating circuitry (see Col 8 Lines 35-48), or to store a mode value of a second state that at least partially disables the gating circuitry for at least a portion of the array of storage cells.
As to claim 18, He discloses a method of operating a memory device (see Fig 1), the memory device comprising
an array of storage cells (see Fig 1 Ref 105), each storage cell coupled to one of multiple bitlines (see Fig 1 Ref 115) and one of multiple local wordlines (see Fig 1 Ref 110), and wherein
groups of the multiple local wordlines (see Col 7 Lines 39-51) are activated by master wordlines (see Fig 1 Ref XADD),
the method comprising: receiving wordline address information (see Fig 1 Ref AREF) to activate an addressed wordline (see Fig 7 Ref 725); selectively suppressing activation of the addressed wordline (see Fig 7 Ref SKIP) during a refresh operation (see Fig 7 Ref 720) within a current refresh period (see Fig 7 Ref N+2) based on a timing of an activate command associated with the addressed wordline (see Fig 6 Ref ACT).
As to claim 19, He discloses the method of claim 18.
Claim 19 recites substantially the same limitations as claim 2.
All the limitations of claim 19 have already been disclosed by He in claim 2 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over He, US 10790005 B1, in view of Smith, US 20190348102 A1.
As to claim 20, He discloses the method of claim 18, further comprising:
incrementing a refresh counter through all wordline addresses associated with the array of storage cells within a refresh interval (see Col 18 Lines 25-36); and initiating a refresh operation for a given wordline corresponding to an incremented address in response to each increment of the refresh counter (see Col 18 Lines 25-36).
He does not appear to disclose that is no more than half a retention time associated with the array of storage cells
Smith discloses that is no more than half a retention time associated with the array of storage cells (see Smith Fig 3A Refs 32ms and 8ms; The minimum disclosed retention time is 32ms, and 8ms is less than half that value.)
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a method, as disclosed by He, may implement particular refresh times, as disclosed by Smith. The inventions are well known variants of schemas for activating wordlines and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Smith’s attempt to improve refresh timings (see Smith Para [0018]).
Allowable Subject Matter
Claim(s) 3-8 and 13-17 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not appear to disclose (as recited in claim 3):
individual ones of the set of one-bit latches are to store a flag bit in response to a corresponding local wordline being activated in response to an activate command; and wherein the gating circuitry is responsive to detection of a stored flag bit associated with a selected one of the set of one-bit latches to selectively suppress activation of the given one of the master wordlines by the master wordline driver.
The prior art does not appear to disclose (as recited in claim 13):
individual ones of the set of one-bit latches are to store a flag bit upon a corresponding one of the multiple local wordlines being activated in response to an activate command; and wherein the gating circuitry is responsive to detection of a stored flag bit associated with a selected one of the set of one-bit latches to selectively suppress activation of the given one of the master wordlines by the master wordline driver.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ahn, US 20240079042 A1 discloses a refresh counter.
Seo, US 20240144988 A1 discloses gating circuitry.
Kim, US 20250246224 A1 discloses storing a flag bit.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 03/17/2026