DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed September 22, 2026.
Claims 1-20 are pending. Claims 1 and 12 are amended. Claims 18-20 are new. Claims 1 and 12 are independent.
Continued Examination Under 37 CFR 1.114 After Final Rejection
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 22, 2026 has been entered.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on September 24, 2026. This IDS has been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Loh et al. (U.S. 2017/0125119; hereinafter “Loh”) in view of Ide et al. (U.S. 2011/0057819; hereinafter “Ide”) and Kang (U.S. 2026/0047482).
Regarding independent claim 1, Loh teaches a memory device (Fig. 10), comprising:
a stacked memory comprising a plurality of memory chips (Fig. 10: 810-840), wherein each memory chip comprises:
at least one memory cell array (see page 3, par. 0047);
a chip identification device (Fig. 6: 142/620) coupled to the at least one memory cell array (see page 3, par. 0047); and
a signal path switch (Fig. 6: 640) coupled to the chip identification device (Fig. 6: 142/620);
a plurality of conductive vias penetrating through the stacked memory (see page 3, par. 0044); and
a memory controller coupled to the stacked memory (see page 8, par. 0104).
However, Loh is silent with respect to wherein the signal path switch functions to switch on or switch off the conductive vias.
Similar to Loh, Ide teaches a memory device (Fig. 1), comprising a stacked memory comprising a plurality of memory chips (Fig. 1: CCs).
Furthermore, Ide teaches a signal path switch (Fig. 4: 200 and 100-108) and a plurality of conductive vias penetrating through the stacked memory (Fig. 1: TSV), wherein the signal path switch functions to switch on or switch off the conductive vias (see page 3, par. 0040-0041).
Since Ide and Loh are from the same field of endeavor, the teachings described by Ide would have been recognized in the pertinent art of Loh.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Ide with the teachings of Loh for the purpose of reduce chip area, see Ide’s page 1, par. 0010.
However, the combination is silent with respect to the memory controller comprises a control unit and an arithmetic logic unit coupled to the control unit.
Similar to the combination, Kang teaches a stack of memory array die (see page 1, par. 0004).
Furthermore, Kang teaches a memory device comprising a memory controller (Fig. 2A: 210) comprising a control unit (Fig. 2A: 214) and an arithmetic logic unit (“arithmetic logic unit,” see page 4, par. 0035) coupled to the control unit.
Since Kang, Ide and Loh are from the same field of endeavor, the teachings described by Kang would have been recognized in the pertinent art of Loh in combination with Ide.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kang with the teachings of Loh in combination with Ide for the purpose of improve semiconductor IC device architecture, see Kang’s page 4, par. 0034.
Regarding claim 2, Loh in combination with Ide and Kang teaches the limitations with respect to claim 1.
Furthermore, Loh teaches wherein the chip identification device comprises an identification register (Fig. 6: 611, 612 and 620).
Regarding claim 3, Loh in combination with Ide and Kang teaches the limitations with respect to claim 2.
Furthermore, Loh teaches wherein the identification register comprises a fuse (Fig. 6: 611 and 612), a one-time programmable memory, a nonvolatile memory, or a combinations thereof.
Regarding claim 4, Loh in combination with Ide and Kang teaches the limitations with respect to claim 1.
Furthermore, Loh teaches wherein the memory chips are nonvolatile memory chips or volatile memory chips (see page 3, par. 0047).
Regarding claim 5, Loh in combination with Ide and Kang teaches the limitations with respect to claim 4.
Furthermore, Loh teaches wherein the nonvolatile memory chips comprise static random-access memories, ferroelectric random-access memories, read-only memories, flash memories, magnetoresistive random-access memories, or combinations thereof (see page 3, par. 0047).
Regarding claim 6, Loh in combination with Ide and Kang teaches the limitations with respect to claim 4.
Furthermore, Loh teaches wherein the volatile memory chips comprise random-access memories, dynamic random-access memories (see page 3, par. 0047), static random-access memories, or combinations thereof.
Regarding claim 7, Loh in combination with Ide and Kang teaches the limitations with respect to claim 1.
Furthermore, Loh teaches a plurality of bumps disposed between the conductive vias and the memory controller (see page 3, par. 0044).
Regarding claim 8, Loh in combination with Ide and Kang teaches the limitations with respect to claim 7.
Furthermore, Loh teaches wherein the bumps are micro bumps, hybrid bumps, bonding pads, or combination thereof (see page 4-5, par. 0063-0064).
Regarding claim 9, Loh in combination with Ide and Kang teaches the limitations with respect to claim 1.
Furthermore, Loh teaches a plurality of bumps or a plurality of bonding pads disposed between two adjacent memory chips (see page 3, par. 0044).
Regarding claim 10, Loh in combination with Ide and Kang teaches the limitations with respect to claim 1.
Furthermore, Loh teaches wherein each memory chip further comprises an input/output circuit coupled between the chip identification device and the memory cell array (Fig. 5: MS/SLV classification circuit).
Regarding claim 11, Loh in combination with Ide and Kang teaches the limitations with respect to claim 1.
Furthermore, Loh teaches control circuits respectively coupled between the chip identification devices of the memory chips and the memory controller (Fig. 10: 802).
Regarding claim 18, Loh in combination with Ide and Kang teaches the limitations with respect to claim 1.
Furthermore, Kang teaches wherein the memory controller further comprises a static random-access memory coupled to the control unit and the arithmetic logic unit (see page 4, par. 0035).
Regarding claim 19, Loh in combination with Ide and Kang teaches the limitations with respect to claim 1.
Furthermore, Kang teaches wherein the memory controller further comprises a processing peripheral circuit coupled to the stacked memory (see page 4, par. 0035).
Regarding claim 20, Loh in combination with Ide and Kang teaches the limitations with respect to claim 1.
Furthermore, Kang teaches wherein the memory controller further comprises a static random-access memory coupled to the control unit and the arithmetic logic unit and a processing peripheral circuit coupled to the stacked memory (see page 4, par. 0035).
Claims 12 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Loh et al. (U.S. 2017/0125119; hereinafter “Loh”) in view of Zhang (U.S. 2025/0192110), Ide et al. (U.S. 2011/0057819; hereinafter “Ide”) and Kang (U.S. 2026/0047482).
Regarding independent claim 12, Loh teaches a method for adjusting a signal transmission (see page 7, par. 0096), the method comprising:
receiving a memory device (Fig. 10) comprising a stacked memory, a plurality of conductive vias (see page 3, par. 0044) penetrating through the stacked memory (Fig. 10: 810-840), and a memory controller coupled to the stacked memory (see page 8, par. 0104), wherein the stacked memory comprises a plurality of memory chips (Fig. 10: 810-840), each memory chip comprises at least one memory cell array (see page 3, par. 0047), a chip identification device (Fig. 6: 142/620) coupled to the at least one memory cell array (see page 3, par. 0047), and a signal path switch (Fig. 6: 640) coupled to the chip identification device (Fig. 6: 142/620), and the conductive vias respectively allow a signal to transmit (see page 3, par. 0042).
However, Loh is silent with respect to wherein the signal path switch functions to switch on or switch off the conductive vias, detecting a first conductive via of the conductive vias for transmitting a first signal is damaged, wherein a damage location of the first conductive via is in a first memory chip of the memory chips, reading a first chip identification of the first memory chip by the memory controller, and adjusting a transmission of the first signal by the memory controller to transmit the first signal through a second conductive via of the conductive vias.
Similar to Loh, Zhang teaches a method for adjusting a signal transmission (see pages 6-7, par. 0095-0096), the method comprising receiving a memory device comprising a stacked memory (see Abstract), and a plurality of conductive vias penetrating through the stacked memory (see Abstract).
Furthermore, Zhang teaches detecting a first conductive via of the conductive vias for transmitting a first signal is damaged (see pages 6-7, par. 0096), wherein a damage location of the first conductive via is in a first memory chip of the memory chips (see page 7, par. 0100), reading a first chip identification of the first memory chip by the memory controller (see page 6, par. 0091), and adjusting a transmission of the first signal by the memory controller to transmit the first signal through a second conductive via of the conductive vias (see page 6, par. 0095).
Since Zhang and Loh are from the same field of endeavor, the teachings described by Zhang would have been recognized in the pertinent art of Loh.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Zhang with the teachings of Loh for the purpose of reduce parasitic resistance and improve transmission speed and performance, see Zhang’s page 20, par. 0249.
However, the combination is silent with respect to wherein the signal path switch functions to switch on or switch off the conductive vias.
Similar to the combination, Ide teaches a memory device (Fig. 1), comprising a stacked memory comprising a plurality of memory chips (Fig. 1: CCs).
Furthermore, Ide teaches a signal path switch (Fig. 4: 200 and 100-108) and a plurality of conductive vias penetrating through the stacked memory (Fig. 1: TSV), wherein the signal path switch functions to switch on or switch off the conductive vias (see page 3, par. 0040-0041).
Since Ide, Zhang and Loh are from the same field of endeavor, the teachings described by Ide would have been recognized in the pertinent art of Loh in combination with Zhang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Ide with the teachings of Loh in combination with Zhang for the purpose of reduce chip area, see Ide’s page 1, par. 0010.
However, the combination is silent with respect to the memory controller comprises a control unit, and an arithmetic logic unit coupled to the control unit.
Similar to the combination, Kang teaches a stack of memory array die (see page 1, par. 0004).
Furthermore, Kang teaches a memory device comprising a memory controller (Fig. 2A: 210) comprising a control unit (Fig. 2A: 214) and an arithmetic logic unit (“arithmetic logic unit,” see page 4, par. 0035) coupled to the control unit.
Since Kang, Ide, Zhang and Loh are from the same field of endeavor, the teachings described by Kang would have been recognized in the pertinent art of Loh in combination with Zhang and Ide.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kang with the teachings of Loh in combination with Zhang and Ide for the purpose of improve semiconductor IC device architecture, see Kang’s page 4, par. 0034.
Regarding claim 16, Loh in combination with Zhang, Ide and Kang teaches the limitations with respect to claim 12.
Furthermore, Zhang teaches wherein the adjusting the transmission of the first signal by the memory controller to transmit the first signal through the second conductive via of the conductive vias (see pages 6-7, par. 0095-0096) comprises:
switching of the first conductive via by the signal path switch corresponding to the first conductive via (see pages 6-7, par. 0095 and par. 0100); and
switching on the second conductive via by the signal path switch corresponding to the second conductive via (see pages 6-7, par. 0095 and par. 0100).
Regarding claim 17, Loh in combination with Zhang, Ide and Kang teaches the limitations with respect to claim 12.
Furthermore, Zhang teaches transmitting a second signal through the first conductive via, wherein the second signal is transmitted to a second memory chip stacked between the first memory chip and the memory controller (see pages 6-7, par. 0095 and par. 0100).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Loh, Zhang, Ide and Kang as applied to claim 12 above, and further in view of Veches (U.S. 2015/0348647).
Regarding claim 13, Loh in combination with Zhang, Ide and Kang teaches the limitations with respect to claim 12.
However, the combination is silent with respect to setting a current reference value in the chip identification device of each memory chip, wherein the detecting the first conductive via of the conductive vias for transmitting the first signal is damaged comprises: comparing an output current value of the first signal through the first conductive via to the current reference value of the chip identification device of the first memory chip, wherein the output current value is different from the current reference value.
Veches teaches setting a current reference value (“known good current,” see page 3, par. 0038) in the chip identification device (see page 1, par. 0014) of each memory chip,
wherein the detecting the first conductive via of the conductive vias for transmitting the first signal is damaged comprises:
comparing an output current value of the first signal through the first conductive via to the current reference value of the chip identification device of the first memory chip, wherein the output current value is different from the current reference value (see page 3, par. 0038).
Since Veches, Kang, Zhang, Ide and Loh are from the same field of endeavor, the teachings described by Veches would have been recognized in the pertinent art of Loh in combination with Zhang, Ide and Kang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Veches with the teachings of Loh in combination with Zhang, Ide and Kang for the purpose of obtain an apparatus for detecting a via stack fault that even connections with no external access can be tested, see Veches’s page 3, par. 0042.
Regarding claim 14, Loh in combination with Zhang, Ide and Kang teaches the limitations with respect to claim 12.
However, the combination is silent with respect to setting a resistance reference value in the chip identification device of each memory chip, wherein the detecting the first conductive via of the conductive vias for transmitting the first signal is damaged comprises: comparing a resistance of the first conductive via to the resistance reference value of the chip identification device of the first memory chip, wherein the resistance is different from the resistance reference value.
Veches teaches setting a resistance reference value in the chip identification device of each memory chip (“expected resistance,” see page 3, par. 0036),
wherein the detecting the first conductive via of the conductive vias for transmitting the first signal is damaged comprises:
comparing a resistance of the first conductive via to the resistance reference value of the chip identification device of the first memory chip, wherein the resistance is different from the resistance reference value (see page 3, par. 0036-0037).
Since Veches, Kang, Zhang, Ide and Loh are from the same field of endeavor, the teachings described by Veches would have been recognized in the pertinent art of Loh in combination with Zhang, Ide and Kang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Veches with the teachings of Loh in combination with Zhang, Ide and Kang for the purpose of obtain an apparatus for detecting a via stack fault that even connections with no external access can be tested, see Veches’s page 3, par. 0042.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Loh, Zhang, Ide and Kang as applied to claim 12 above, and further in view of Shim (U.S. 2016/0299190).
Regarding claim 15, Loh in combination with Zhang, Ide and Kang teaches the limitations with respect to claim 12.
However, the combination is silent with respect to setting a voltage reference value in the chip identification device of each memory chip, wherein the detecting the first conductive via of the conductive vias for transmitting the first signal is damaged comprises: comparing a voltage of the first conductive via to the voltage reference value of the chip identification device of the first memory chip, wherein the voltage is different from the voltage reference value.
Shim teaches setting a voltage reference value in the chip identification device of each memory chip (“reference level,” see page 1, par. 0012),
wherein the detecting the first conductive via of the conductive vias for transmitting the first signal is damaged comprises:
comparing a voltage of the first conductive via to the voltage reference value of the chip identification device of the first memory chip, wherein the voltage is different from the voltage reference value (see page 1, par. 0012).
Since Shim, Kang, Zhang, Ide and Loh are from the same field of endeavor, the teachings described by Shim would have been recognized in the pertinent art of Loh in combination with Zhang, Ide and Kang.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Shim with the teachings of Loh in combination with Zhang, Ide and Kang for the purpose of guarantee signal transmission quality of the through-silicon vias, see Shim’s page 1, par. 0006.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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