DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
2. Claim 9, claim 12 and claim 15 objected to beca0075se of the following informalities: "silicon nitrite" should read "silicon nitride". Appropriate correction is required.
Examiner will exam as “silicon nitride”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
3. Claims 1-5, claim 9, claim 12, claim 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US20060166458A1), in view of Cho (US 20090098735A1) and further in view of Jain (US 5741626 A).
As to claim 1, Cheng teaches that a shallow trench isolation (STI) structure for semiconductor devices (abstract), that a method for forming an isolation structure in a semiconductor device, said method comprising: forming an oxide layer over a substrate; forming a polish stop layer over said oxide layer; depositing a silicon layer over said polish stop layer (claim 14). Cheng teaches in method for forming shallow trench isolation structures, that a method is provided for forming an isolation structure in a semiconductor device. The method includes forming a polishing resistant layer over a substrate, forming a buffer layer over the polishing resistant layer, forming a trench with smooth sidewalls by etching through the buffer layer and the polishing resistant layer and into the substrate, the smooth sidewalls formed of portions of the substrate, the polishing resistant layer and the buffer layer (para. 6). The method as in claim 1 wherein said polishing further removes said buffer layer from over said polishing resistant layer (claim 5). Another method provides for forming an oxide layer over a substrate, forming a polish stop layer over the oxide layer (para. 7). Another exemplary method for forming an Isolation structure in a semiconductor device provides forming a polishing resistant layer over a substrate, depositing a buffer layer over the polishing resistant layer, defining a trench region, forming a trench with straight sidewalls by etching through the buffer layer and the polishing resistant layer (para. 8).
The teachings of Cheng differ from that of the instantly claimed invention in that Cheng does not teach explicitly that forming a photoresist pattern on an anti-reflective layer on a wafer; forming an oxide layer on the anti-reflective layer and the photoresist pattern, wherein the oxide layer has a protruding portion overlapping the photoresist pattern; forming a polish stop layer along a top surface of the oxide layer; forming a buffer layer on the polish stop layer; polishing the buffer layer such that at least a portion of the buffer layer is removed and the polish stop layer is exposed; and etching the buffer layer, the polish stop layer and the oxide layer such that the photoresist pattern is exposed.
Cho teaches that a method of forming an isolation layer in a semiconductor device comprising: sequentially forming an insulating layer and an anti-reflective layer over a semiconductor substrate having an isolation area for defining an active region; and then forming a photoresist pattern over the anti-reflective layer; and then forming an insulating layer pattern over the isolation area by performing an etch process using the photoresist pattern as an etch mask; and then forming a polysilicon layer around the insulating layer pattern (claim 1). The method of claim 1, wherein the insulating layer comprises a silicon oxide layer (claim 2). As illustrated in example FIG. 2A, Insulating layer 12 and anti-reflective layer 13 are sequentially formed on and/or over semiconductor substrate 11. Photoresist pattern 14 is then formed on and/or over anti-reflective layer 13. Anti-reflective layer 13 is provided to prevent diffused reflection and preferably includes a bottom anti-reflective coating (BARC) layer. Anti-reflective layer 13 is formed by coating. Insulating layer 12 includes a silicon oxide layer (para. 15). Cho further teaches that etch process is performed using photoresist pattern 5 as an etch mask until a surface of substrate 1 is exposed. BARG layer 4, silicon oxide layer 3 and silicon nitride layer 2 are partially removed by the etch process (para. 4).
Jang teaches that when the oxide film 160 is filled into the through hole H, the depth of the through hole H filled with the first material 150 can be controlled to produce an overhang state, so that the oxide film 160 contains a cavity (para. 10). As shown in Figures 6 and 7, a groove photoresist pattern 220 can be formed on and/or over the substrate containing the oxide film 160 (para. 11).
Cheng (Fig. 1-4)
Cho's layer (Fig. 1A)
Jain's layer (Fig. 1-11)
instant layer (Fig. 6)
substrate 11
substrate 12
wafer 110
insulating layer 12
second dielectric layer (or oxide layer) 20
silicon oxide layer 150
anti-reflective layer 13
anti-reflective coating ARC 18 (Ta3N5 dielectric layer)
anti-reflective layer 130
photoresist pattern 14
photoresist material 48
photoresist pattern 140
Cho's layer (Fig. 18)
Instant layer (Fig. 6)
substrate 1
substrate 1
water 110
polishing resistant layer (nitride) 5
silicon nitride layer 2
polish stop layer (Ta3N5 or )
polish stop layer 160 (Si3N4)
1st dielectric layer (oxide) 3
silicon oxide layer 3
first dielectric layer (or oxide layer) 16
silicon oxide layer 150
bottom anti-reflective coating (BARG) layer 4
anti reflective layer 130
photoresist pattern 5
photoresist material 22
photoresist pattern 140
insulator (oxide maybe TEOS oxide) 15
oxide layer 6
first dielectric layer (TEOS)
buffer layer (TEOS oxide)170
Buffer layer (Si or polysilicon or amorphous Si layer)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to combine Cheng, Cho and Jain before the effective filing date of the claimed invention to incorporate known lithographic anti reflection, photoresist patterning and overhang state techniques into Cheng’s polishing planarization process to arrive at the claimed invention. It would have been prima facie obvious for one of ordinary skill in the art to modify Cheng with Cho and Jain because lithographic patterning using anti-reflective layers and photoresist was conventionally combined with oxide deposition and CMP planarization. One of ordinary skill in the art would have a reasonable expectation of success to obtain predictable semiconductor structures.
As to claim 2, Cheng, Cho and Jain teach as applied in claim 1 above. Cheng further teaches that the polishing resistant layer is a silicon nitride layer (claim 2), the polishing operation continues until top surface 17 of polishing resistant layer 5 is exposed (para. 20). Cho further teaches that the insulating layer comprises a silicon oxide layer (claim 2). Forming the polysilicon layer comprises forming the polysilicon layer such that a portion of the insulating layer pattern protrudes from the polysilicon layer (claim 8).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to perform polishing until exposure of the polish stop layer located on protruding oxide region to achieve controlled endpoint detection and improve planarity.
As to claim 3, Cheng, Cho and Jain teach as applied to claim 2 above. Cheng teaches that polishing further removes said buffer layer from over said polishing resistant layer (claim 5). Cho teaches that Insulating layer 12 includes a silicon oxide layer (para.15), that forming an insulating layer pattern in the isolation region by performing a first etching process using the photoresist pattern as an etching mask; and then forming a polysilicon layer over the semiconductor substrate to surround the insulating layer pattern such that a portion of the insulating layer pattern protrudes from the uppermost surface of the polysilicon layer (claim 10).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention that continued polishing removes the upper portion of buffer material (silicon oxide) in regions not protected by the photoresist -defined pattern, producing selective top removal.
As to claim 4, Cheng, Cho and Jain teach as applied in claim 2 above. Cheng teaches that A chemical mechanical polishing operation polishes the deposited silicon layer at a rate faster than the deposited oxide layer to produce an STI with a convex portion extending above the nitride layer (abstract). Cheng further teaches that according to the polishing operation of the invention, however, once buffer layer 7 is exposed during the polishing operation, the material removal rate is greater for buffer layer 7 than for the deposited insulator 15. The polishing operation continues until top surface 17 of polishing resistant layer 5 is exposed. and produces the structure shown in FIG. 4 in which section 21 of STI 19 extends above top surface 17 of polishing resistant layer 5. Polishing resistant layer 5 is not appreciably receded during the polishing operation and serves as the polishing stop layer. After the structure shown in FIG. 4 is formed, a global polishing operation may be used to planarize the structure and produce the planarized structure shown in FIG. 5. FIG. 5 shows STI 19 extending within substrate 1 and STI 19 includes substantially planar STI surface 23 which is co-planar with surrounding surfaces and forms planar top surface 25. Dishing is avoided (para. 20). Polishing resistant layer is a silicon nitride layer (claim 2).
The Co-planar Cheng teaches is between STI surface (oxide) and surrounding surface (including polishing resistant layer (silicon nitride (para. 16)) (Fig. 4). And the coplanar in the instant claim 4 is between the buffer layer (TEOS oxide) not overlapping the photoresist pattern and the top surface of polish stop layer (Si3N4) (Fig. 6).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to terminate CMP at exposure to obtain coplanarity.
As to claim 5, Cheng, Cho and Jain teach as applied in claim 1 above. Cheng further teaches that buffer layer comprises a silicon layer, a polysilicon layer or an amorphous silicon layer (claim 6). Polishing comprises chemical mechanical polishing that further removes said silicon layer from over said polish stop layer, at a rate faster than said deposited oxide layer (claim 15). Cho teaches that forming an insulating layer pattern on and/or over and corresponding to an isolation area of the substrate by performing an etch process using the photoresist pattern as an etch mask, and then forming a polysilicon layer around the insulating layer pattern such that the insulating layer patterns protrudes from the uppermost surface of the polysilicon layer (abstract).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention polishing the buffer layer such that the top surface of the oxide layer overlapping the photoresist pattern becomes recessed and exposed through the polish stop layer.
As to claim 9, Cheng, Cho and Jian teach as applied to claim 1 above. Cheng further teaches that the CMP process typically uses a pad oxide formed over the substrate and a silicon nitride that serves as a polishing-stop layer, formed over the pad oxide (para. 3).
the method as in claim 1, wherein said insulating layer comprises TEOS or an HDP oxide (claim 13).
Thus, selecting silicon nitride for polish stop and TEOS oxide for buffer or insulating layer would have been obvious.
As to claim 12, Cheng, Cho and Jian teach as applied in claim 1 above. Cheng further teaches that a method for forming an isolation structure in a semiconductor device, said method comprising: forming a polishing resistant layer over a substrate (claim 1). The method as in claim 1, wherein said polishing resistant layer is a silicon nitride layer (claim 2). Cheng additionally teaches that the method further provides forming an insulating layer over the buffer layer and filling the trench, and polishing to remove the insulating layer (oxide maybe TEOS oxide (para. 18)) from over the polishing resistant layer (polishing resistant layer 5 may be silicon nitride (para. 16)) using a polishing operation that removes the buffer layer at a rate faster than the deposited insulator (para. 6).
Cho teaches that as illustrated in example FIG. 1A, a method of forming an isolation layer in a semiconductor device may include sequentially forming silicon nitride layer 2, silicon oxide layer 3 and bottom anti-reflective coating (BARC) layer 4 on and/or over semiconductor substrate 1. Silicon nitride layer 2 and silicon oxide layer 3 are formed by chemical vapor deposition (CVD). Photoresist pattern 5 is then formed on and/or BARC 4. Photoresist pattern 5 is provided to discriminate an active area and an inactive area that will be formed on and/or over substrate 1. Photoresist pattern 5 is formed to correspond to the active area in which a prescribed semiconductor device including a transistor will be formed (para. 3). Cho additionally teaches that the method of claim 1, wherein forming the insulating layer pattern comprises selectively etching the anti-reflective layer and the insulating layer using the photoresist pattern as an etch mask until the semiconductor substrate is exposed (claim 5).
Jain teaches that FIG. 4 illustrates that the opening 30 through the photoresist layer 28 is extended through the anti-reflective coating dielectric tantalum nitride layer 18 and the first dielectric layer 16 to expose a top surface of the conductive region 14 (col 4, line 21). it is apparent that there has been provided a method for providing a dielectric tantalum nitride layer to function as an anti-reflective coating (ARC) and/or an etch stop layer and/or a diffusion barrier in a semiconductor structure (col 6, line 61).
it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ Jian's photoresist layer extended through the anti-reflective coating nitride layer in combination with the silicon nitride as polishing resistant layer of Cheng, and silicon nitride or silicon carbon nitride etch stop layers by Cho, because using nitride as anti-reflective coating and/or etch stop layer to improve polishing operation selectivity
As to claim 15, Cheng further teaches that a method for forming an isolation structure in a semiconductor device, said method comprising: forming a polishing resistant layer over a substrate (claim 1). The method as in claim 1, wherein said polishing resistant layer is a silicon nitride layer (claim 2). Buffer layer is formed directly on said silicon nitride layer and said silicon nitride layer is formed directly on a dielectric layer formed directly on said substrate. (claim 3). A shallow trench isolation (STI) structure for semiconductor devices is formed using a deposited silicon layer formed over a polish stop layer formed over an oxide formed on a substrate (abstract). That a method is provided for forming an isolation structure in a semiconductor device. The method includes forming a polishing resistant layer over a substrate, forming a buffer layer over the polishing resistant layer, forming a trench with smooth sidewalls by etching through the buffer layer and the polishing resistant layer and into the substrate, the smooth sidewalls formed of portions of the substrate, the polishing resistant layer and the buffer layer (para. 6). The method as in claim 1 wherein said polishing further removes said buffer layer from over said polishing resistant layer (claim 5). Another method provides for forming an oxide layer over a substrate, forming a polish stop layer over the oxide layer, depositing a silicon layer over the polish stop layer, defining a trench region, forming a trench with straight sidewalls by etching through the silicon layer, the polish stop layer, the oxide layer, and into the substrate in the trench region, the straight sidewalls formed of portions of the substrate, the oxide layer, the polish stop layer and the silicon layer (para. 7). A method for forming an isolation structure in a semiconductor device, said method comprising: forming an oxide layer over a substrate; forming a polish stop layer over said oxide layer; depositing a silicon layer over said polish stop layer (claim 14). Another exemplary method for forming an isolation structure in a semiconductor device provides forming a polishing resistant layer over a substrate, depositing a buffer layer over the polishing resistant layer, defining a trench region, forming a trench with straight sidewalls by etching through the buffer layer and the polishing resistant layer, and into the substrate in the trench region, the straight sidewalls formed of portions of the substrate, the polishing resistant layer and the buffer layer. The method further provides depositing a deposited oxide layer over the buffer layer and filling the trench; and polishing to remove the deposited oxide layer from over the polishing resistant layer using a polishing operation that produces a structure in which portions of the deposited oxide layer extend above a top surface of the polishing resistant layer in the trench region (para. 8). Conventional photoresist materials and patterning techniques may be used to form a pattern in a masking film and a plasma etch process (para. 17).
Jain teaches that the dielectric tantalum nitride layer 18 is deposited on top of the conductive region 14 as illustrated in FIG. 9. A dielectric layer 16 which is analogous to the dielectric layer 16 of FIG. 1 is then deposited overlying the dielectric tantalum nitride layer 18. A second etch stop layer or anti-reflective coating layer 42 is then deposited overlying the first dielectric layer 16. Layer 42 may be made of dielectric tantalum nitride (Ta3 N5) or may be made of other dielectric anti-reflective coatings such as silicon rich silicon nitride. An opening 44 is etched through layer 42 using conventional photolithographic and etch processing (col 5, line 39). After formation of the opening 44 as illustrated in FIG. 9, a second dielectric layer 20 is deposited overlying the opening 44 and the layer 42. Dielectric layer 20 in FIG. 9 is analogous to the dielectric layer 20 of FIG. 1. A polish stop layer 46 is then deposited overlying a top portion of the dielectric layer 20. The polish stop layer 46 may be formed from tantalum nitride (Ta3 N5) or may be formed by any polish stop material which is suitable for stopping a chemical mechanical polishing (CMP) operation. It is important to note that any one layer, several layers, or all of the layers 18, 42, and 46 may be used to provide anti-reflective properties during the formation of the semiconductor structure 40 (col 5, line 52). FIG. 10 illustrates that a photoresist layer 48 is formed over a top of the polish stop layer 46. The photoresist layer 48 of FIG. 10 is analogous to the photoresist layer 22 of FIG. 1. Therefore, the opening 24 of FIG. 1 is analogous to the opening 50 of FIG. 10. It is important to note that the opening 50 through the photoresist layer 48 has a width which is greater than a width of the opening 44 as illustrated in FIG. 10 (col 5, line 64). An etch operation is used while photoresist mask 66 is in place to etch exposed portions of the second dielectric layer 20 and the dielectric tantalum nitride layer within opening 68. Further, the etch will expose portions of first dielectric layer 16 within first portion 64 of an opening to the same etch chemistry (col 6, line 45).
Cho teaches that as illustrated in example FIG. 1A, a method of forming an isolation layer in a semiconductor device may include sequentially forming silicon nitride layer 2, silicon oxide layer 3 and bottom anti-reflective coating (BARC) layer 4 on and/or over semiconductor substrate 1. Silicon nitride layer 2 and silicon oxide layer 3 are formed by chemical vapor deposition (CVD). Photoresist pattern 5 is then formed on and/or BARC 4. Photoresist pattern 5 is provided to discriminate an active area and an inactive area that will be formed on and/or over substrate 1. Photoresist pattern 5 is formed to correspond to the active area in which a prescribed semiconductor device including a transistor will be formed (para. 3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to combine Cheng, Cho and Jain before the effective filing date of the claimed invention to incorporate known lithographic anti reflection using nitride layer, photoresist patterning and overhang state techniques by Cho and Jain into Cheng’s polishing planarization process to arrive at the claimed invention. It would have been prima facie obvious for one of ordinary skill in the art to modify Cheng with Cho and Jain because lithographic patterning using anti-reflective layers and photoresist was conventionally combined with oxide deposition and CMP planarization. One of ordinary skill in the art would have a reasonable expectation of success to obtain predictable semiconductor structures.
As to claim 16, Cheng, Cho and Jain teach as applied in claim 15 above. Cheng further teaches that the polishing resistant layer is a silicon nitride layer (claim 2), the polishing operation continues until top surface 17 of polishing resistant layer 5 is exposed (para. 20). Cho further teaches that the insulating layer comprises a silicon oxide layer (claim 2). Forming the polysilicon layer comprises forming the polysilicon layer such that a portion of the insulating layer pattern protrudes from the polysilicon layer (claim 8).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to perform polishing until exposure of the polish stop layer located on protruding oxide region to achieve controlled endpoint detection and improve planarity.
As to claim 17, Cheng, Cho and Jain teach as applied to claim 16 above. Cheng further teaches that forming an insulating layer (TEOS (claim 13)) over said buffer layer and filling said trench; and polishing to remove said insulating layer from over said polishing resistant layer (silicon nitride (claim 19)) using a polishing operation that removes said buffer layer at a rate faster than said insulating layer. Cheng additionally teaches that the method as in claim 1, wherein said polishing produces a structure in which portions of said insulating layer (TEOS (claim 13)) extend above a top surface of said polishing resistant layer (silicon nitride (claim 19)) over said trench (claim 10). The method as in claim 10, further comprising planarizing after said polishing and removing said polishing resistant layer after said planarizing (claim 11). According to the polishing operation of the invention, however, once buffer layer 7 is exposed during the polishing operation, the material removal rate is greater for buffer layer 7 than for the deposited insulator 15. The polishing operation continues until top surface 17 of polishing resistant layer 5 is exposed (para. 20). The characteristics of the etch process or processes are controlled to produce an anisotropic etch (para. 17).
Cheng’s insulating layer (TEOS) is equivalent to the buffer layer of the instant claim. Cheng’s polishing resistant layer (Silicon nitride) is equivalent to the polish stop layer of the instant claim.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to continue polishing beyond initial exposure to remove remaining upper buffer portions.
As to claim 18, Cheng, Cho and Jain teach as applied in claim 16 above. Cheng teaches that a chemical mechanical polishing operation polishes the deposited silicon layer at a rate faster than the deposited oxide layer to produce an STI with a convex portion extending above the nitride layer (abstract). Cheng further teaches that according to the polishing operation of the invention, however, once buffer layer 7 is exposed during the polishing operation, the material removal rate is greater for buffer layer 7 than for the deposited insulator 15. The polishing operation continues until top surface 17 of polishing resistant layer 5 is exposed. and produces the structure shown in FIG. 4 in which section 21 of STI 19 extends above top surface 17 of polishing resistant layer 5. Polishing resistant layer 5 is not appreciably receded during the polishing operation and serves as the polishing stop layer. After the structure shown in FIG. 4 is formed, a global polishing operation may be used to planarize the structure and produce the planarized structure shown in FIG. 5. FIG. 5 shows STI 19 extending within substrate 1 and STI 19 includes substantially planar STI surface 23 which is co-planar with surrounding surfaces and forms planar top surface 25. Dishing is avoided (para. 20). Polishing resistant layer is a silicon nitride layer (claim 2).
The Co-planar Cheng teaches is between STI surface (oxide) and surrounding surface (including polishing resistant layer (silicon nitride (para. 16)) (Fig. 4). And the coplanar in the instant claim 18 is between the buffer layer (TEOS oxide) not overlapping the photoresist pattern and the top surface of polish stop layer (Si3N4) (Fig. 6).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to terminate CMP at exposure to obtain coplanarity.
4. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US20060166458A1), in view of Cho (US 20090098735A1) and Jain (US 5741626 A), and further in view of Aktas (US10755986B2).
Cheng, Cho and Jain teach as applied to claim 1 above. The teaching of Cheng, Cho and Jian differ from that of the instantly claimed invention in that they did not teach exactly that the method of claim 1, wherein the buffer layer has a thickness in a range from 50 nanometers to 60 nanometers after polishing the buffer layer.
Aktas teaches that in order to planarize the polycrystalline ceramic substrate, a dielectric layer (e.g., oxide) can be deposited and then a material removal process, (e.g., a CMP process) can be used to remove most or all of the deposited dielectric, with any crevices in the substrate being filled with the deposited dielectric. In some embodiments, the dielectric can comprise silicon dioxide, TEOS (col 14, line 8). The adhesion layer 112 comprises a tetraethyl orthosilicate (TEOS) layer on the order of 1,000 Å in thickness. In other embodiments, the thickness of the adhesion layer varies, for example, from 100 Å to 2,000 Å (col 6, line 64).
100 Å to 2,000 Å which is equal to 10nm to 200nm. This range overlap s 50nm to 60nm.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to maintain the buffer layer has a thickness in a range from 50 nanometers to 60 nanometers after polishing the buffer layer in the combined Cheng, Cho and Jain with Aktas, because all references are directed to semiconductor CMP processes. Aktas explicitly teaches that to planarize the substrate, the thickness of the tetraethyl orthosilicate (TEOS) layer is from 10nm to 200nm.
Further, “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists” (See MPEP 2144.05(I)).
5. Claim 7 and claim 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US20060166458A1), in view of Cho (US 20090098735A1) and Jain (US 5741626 A), and further in view of Moeggenborg (US6974777B2).
As to claim 7, Cheng, Cho and Jain teach as applied to claim 1 above. The teaching of Cheng, Cho and Jain differ from that of the instantly claimed invention in that they did not teach exactly that the method of claim 1, wherein polishing the buffer layer comprises dispensing a slurry and a surfactant.
Moeggenborg teaches in CMP compositions for low-k dielectric materials, that a method of polishing low dielectric constant inorganic polymer layers comprising zironica abrasive and a nonionic, anionic, cationic, or amphoteric surfactant, which purportedly acts to stabilize the polishing slurry against settling (col 2, line 19). Similar blanket wafer substrates containing tantalum (Ta), silicon dioxide (TEOS), or carbon-doped silicon dioxide (CDO) were polished with different polishing compositions (Polishing Compositions 3A-3E). Each of the polishing compositions contained 12 wt. % colloidal silica, 0.10 wt. % benzotriazole, 0.30 wt. % acetic acid, 3 wt. % hydrogen peroxide, and 200 ppm surfactant with a pH of about 10 (col 10, line 57). And Surfactants are commonly used in chemical-mechanical polishing compositions to function as dispersants or flocculating agents (col 1, line 66).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention employ the slurry composition of Moeggenborg during Cheng’s chemical mechanical polishing process because surfactant function as dispersants and stabilize the polishing slurry.
As to claim 19, Cheng, Cho and Jain teach as applied to claim 15 above. The teaching of Cheng, Cho and Jain differ from that of the instantly claimed invention in that they did not teach exactly that the method of claim 1, wherein polishing the buffer layer comprises dispensing a slurry and a surfactant.
Moeggenborg teaches in CMP compositions for low-k dielectric materials, that a method of polishing low dielectric constant inorganic polymer layers comprising zironica abrasive and a nonionic, anionic, cationic, or amphoteric surfactant, which purportedly acts to stabilize the polishing slurry against settling (col 2, line 19). Similar blanket wafer substrates containing tantalum (Ta), silicon dioxide (TEOS), or carbon-doped silicon dioxide (CDO) were polished with different polishing compositions (Polishing Compositions 3A-3E). Each of the polishing compositions contained 12 wt. % colloidal silica, 0.10 wt. % benzotriazole, 0.30 wt. % acetic acid, 3 wt. % hydrogen peroxide, and 200 ppm surfactant with a pH of about 10 (col 10, line 57). And Surfactants are commonly used in chemical-mechanical polishing compositions to function as dispersants or flocculating agents (col 1, line 66).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention employ the slurry composition of Moeggenborg during Cheng’s chemical mechanical polishing process because surfactant function as dispersants and stabilize the polishing slurry.
6. Claim 8 and claim 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US20060166458A1), Cho (US 20090098735A1), Jain (US 5741626 A), in view of Moeggenborg (US6974777B2) and in further view of Granstrom (US11999877B2).
As to claim 8, Cheng, Cho, Jain and Moeggenborg teach as applied to claim 7 above. The teaching of Cheng, Cho, Jain and Moeggenborg differ from that of the instantly claimed invention in that they did not teach that the method of claim 7, wherein a friction of the polish stop layer against the slurry and a friction of the buffer layer against the slurry are different.
Granstrom teaches in silicon nitride chemical mechanical polishing slurry with silicon nitride removal rate enhancers and methods of use thereof, that silicon nitride (SiN) chemical-mechanical polishing (CMP) compositions with SiN removal rate enhancers. The SiN CMP compositions increase the SiN polishing rate while suppressing the tetratethylorthosilicate (TEOS) polishing rate, thus providing a high SiN/TEOS selectivity ratio and reducing any defects on the surfaces of polished substrates (abstract). The method results in a SiN:TEOS removal rate selectivity ratio of greater than about 40 (claim 15). Granstrom further teaches that surfactants, that purportedly forms bonds with the surface of the silica or copper substrate and suppresses formation of silica precipitates and copper staining (col 2, line 26).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention employ the high SiN/TEOS selectivity by suppressing the removal rate of Granstrom into Cheng, Cho, Jain and Moeggenborg’s CMP process in order to improve layer selectivity.
As to claim 20, Cheng, Cho, Jain and Moeggenborg teach as applied to claim 19 above. The teaching of Cheng, Cho, Jain and Moeggenborg differ from that of the instantly claimed invention in that they did not teach that the method of claim 7, wherein a friction of the polish stop layer against the slurry and a friction of the buffer layer against the slurry are different.
Granstrom teaches in silicon nitride chemical mechanical polishing slurry with silicon nitride removal rate enhancers and methods of use thereof, that silicon nitride (SiN) chemical-mechanical polishing (CMP) compositions with SiN removal rate enhancers. The SiN CMP compositions increase the SiN polishing rate while suppressing the tetratethylorthosilicate (TEOS) polishing rate, thus providing a high SiN/TEOS selectivity ratio and reducing any defects on the surfaces of polished substrates (abstract). The method results in a SiN:TEOS removal rate selectivity ratio of greater than about 40 (claim 15). Granstrom further teaches that surfactants, that purportedly forms bonds with the surface of the silica or copper substrate and suppresses formation of silica precipitates and copper staining (col 2, line 26).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention employ the high SiN/TEOS selectivity by suppressing the removal rate of Granstrom into Cheng, Cho, Jain and Moeggenborg’s CMP process in order to improve layer selectivity.
7. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US20060166458A1), Cho (US 20090098735A1), Jain (US 5741626 A), in view of Moeggenborg (US6974777B2), and further in view of Bauck (The 2nd PacRim International Conference on Planarization/CMP and its Application Technology, November 17–19, 2005, at the COEX in Seoul, Korea).
Cheng, Cho, Jain and Moeggenborg teach as applied to claim 7 above. The teaching of Cheng, Cho, Jain and Moeggenborg differ from that of the instantly claimed invention in that they did not teach exactly that the method of claim 7, wherein the slurry is dispensed at a rate in a range from 50 milliliters to 60 milliliters per minute.
Bauck teaches in Slurry Pump affects on CMP, that the bearingless pumping system (BPS) point of use system tested on the oxide CMP process showed flatter removal rates above 2000 A/min than the peristaltic pump system. Blanket wafer non-uniformity results were less than 4.5% at slurry flow rates ranging from 20mL/min to 280 mL/min. BPS blanket copper removal rates at 50 mL/min were 2500 A/min higher than the peristaltic pumps. Tantalum blanket wafer non-uniformities were less than 5.7% on slurry flow rates ranging from 50 mL/min to 250 mL/min (abstract).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Cheng, Cho, Jain, Moeggenborg and Bauck by having a flow rate between 50-60 ml/min because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (See MPEP 2144.05(I)).
8. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US20060166458A1), Cho (US 20090098735A1), Jain (US 5741626 A), in view of Moeggenborg (US6974777B2), and further in view of Haerle US20150315441A1).
Cheng, Cho, Jain and Moeggenborg teach as applied to claim 7 above. The teaching of Cheng, Cho, Jain and Moeggenborg differ from that of the instantly claimed invention in that they did not teach exactly that the method of claim 7, wherein the surfactant is dispensed at a rate in a range from 200 milliliters to 350 mellites per minute.
Haerle teaches in Polishing slurry including zirconia particles and a method of using the polishing slurry, that FIG. 2 illustrates a depiction of a portion of a polishing apparatus 10. In an embodiment, the polishing apparatus 10 can be used to CMP a target member 14. The polishing apparatus 10 includes a platen 11 and a polishing pad 12 attached to the platen 11. During polishing, a polishing slurry 18 is dispensed from a nozzle 16 onto the polishing pad 12. The polishing slurry 18 can be any one of the polishing slurries as previously herein. The polishing slurry 18 may be dispensed at a rate of approximately 20 mL/minute to approximately 900 mL/minute (para. 56).
In the instant application, polishing the buffer layer comprises dispensing a slurry and a surfactant (claim 7, claim 19, para. 22). Therefore, the examiner interpret that the component of the slurry is NOT separately dispended.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to select a slurry dispensing rate of 300-350ml/min, because slurry flow rate is one of the know CMP parameters. And the 20 to 900 ml/min range fully encompasses 200-350ml/min.
Further, “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists” (See MPEP 2144.05(I)).
9. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US20060166458A1), Cho (US 20090098735A1), Jain (US 5741626 A), in view of Bao ( US20050006340A1), and in further view of Kim (US6927178B2).
Cheng, Cho and Jain teach as applied to claim 1 above.
The teaching of Cheng, Cho and Jain differ from that of the instantly claimed invention in that they did not teach exactly that the method of claim 1, wherein the anti-reflective layer is a dielectric coating film, and a material of the anti-reflective layer comprises carbon.
Bao teaches that a non-nitrogen anti-reflective layer is formed on the dielectric layer (abstract), the non-nitrogen anti-reflective layer is a silicon-rich oxide layer (claim 3), the non-nitrogen anti-reflective layer is a hydrocarbon-containing silicon-rich oxide layer (claim 4).
Kim teaches in Nitrogen-free dielectric anti-reflective coating and hardmask, that the dielectric material comprises silicon and oxygen. In another aspect, the dielectric material forms one or both layers in a dual layer anti-reflective coating (abstract). A method for processing a substrate, comprising: depositing a first anti-reflective layer; and depositing a second anti-reflective layer on the first anti-reflective layer by a process comprising: introducing a processing gas comprising a compound comprising an oxygen-free silane-based compound and an oxygen and carbon containing compound to the processing chamber; and reacting the processing gas to deposit a nitrogen-free dielectric material on the substrate, wherein the nitrogen-free dielectric material comprises at least silicon and oxygen (claim 1). Kim additionally teaches that the extinction coefficient (κ) and the index of refraction (n) of the nitrogen-free dielectric material may be varied as a function of the composition of the gas mixture and processing parameters. It is believed that the amount of Si—H bonds in the deposited material affects the extinction coefficient (κ), and that modification of compositions and processing parameters will allow for control of the amount of Si—H bonds and the optical properties of the deposited material.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form the anti-reflective layer of Cheng’s process using a carbon-containing dielectric materials as taught by Bao and Kim to improve optical properties during lithographic processing.
10. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US20060166458A1), Cho (US 20090098735A1), in view of Jain (US 5741626 A), and in further view of Pas (US8304342B2).
Cheng, Cho and Jain teach as applied to claim 1 above. The teaching of Cheng, Cho and Jain differ from that of the instantly claimed invention in that they did not teach exactly that the method of claim 1, wherein the buffer layer has a thickness in a range from 150 nanometers to 250 nanometers.
Pas teaches in sacrificial CMP etch stop layer, that the second layer of dielectric material 242 may comprise, for example, an oxide based material (e.g., TEOS) formed to a thickness of between about 400 Angstroms and about 2000 Angstroms (col 4, line 38). It can be appreciated that significant resources go into scaling down device dimensions and increasing packing densities. For example, significant man-hours may be required to design such scaled down devices, equipment necessary to produce such devices may be expensive and/or processes related to producing such devices may have to be very tightly controlled and/or be operated under very specific conditions, etc. (col 1, line 41).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the instantly claimed invention to select a buffer layer thickness within the disclosed operating range, including 150nm to 150nm, because layer thickness is one of the variables in the CMP for the purpose of scaled down and tightly control. The 400 to 2000 Angstroms is 40 to 200 nanometers, which overlap the instant claimed 150 to 250 nanometers.
Further, “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists” (See MPEP 2144.05(I)).
Conclusion
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Xin WEN whose telephone number is (571)270-5544. The examiner can normally be reached Monday thru Friday, 7:00am to 4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua L Allen can be reached at 5712703176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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XIN . WEN
Examiner
Art Unit 1713
/X.W./Examiner, Art Unit 1713
/BINH X TRAN/Primary Examiner, Art Unit 1713
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