DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/16/2026 is being considered by the examiner.
Drawings
The drawings submitted on 08/26/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the two ends" in claim 9. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20220254895 A1) in view of Kim et al. (US 20210408254 A1) and Shin et al. (US 20150214341 A1).
Regarding claim 1, Yang discloses a semiconductor device, comprising:
a fin (403); ([0046], Fig. 24)
a gate structure (200) positioned on the fin (403), ([0046], Fig. 24)
impurity regions (301) positioned on two sides of the fin (403); ([0046], Fig. 24)
contacts (101) positioned on the impurity regions (301); ([0069], Fig. 24) and
top conductive layers (107) positioned on the contacts (101), wherein the top conductive layers (107) comprise titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide; ([0099], Fig. 24) wherein
the contacts (101) comprise:
lower portions (101-1) correspondingly positioned on the impurity regions (301);
middle portions (101-3) correspondingly positioned on the lower portions (101-1); and
upper portions (101-5) correspondingly positioned on the middle portions (101-3); wherein a width of the upper portion (101-5) is greater than a width of the middle portion (101-3). ([0108], Fig. 24)
Yang does not disclose:
wherein the gate structure comprises a gate dielectric layer, a gate bottom conductive layer, a gate top conductive layer, and a gate capping layer, wherein the gate dielectric layer is positioned on the fin, the gate bottom conductive layer is positioned on the gate dielectric layer, the gate top conductive layer is positioned on the gate bottom conductive layer, and the gate capping layer is positioned on the gate top conductive layer;
However, Shin discloses:
wherein the gate structure (200) comprises a gate dielectric layer (80c), a gate bottom conductive layer (82), a gate top conductive layer (84), wherein the gate dielectric layer (80c) is positioned on the fin (20c), the gate bottom conductive layer (82) is positioned on the gate dielectric layer (80c), the gate top conductive layer (84) is positioned on the gate bottom conductive layer (82), ([0098]-[0099], Fig. 4B)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yang and Shin for wherein the gate structure comprises a gate dielectric layer, a gate bottom conductive layer, a gate top conductive layer, and a gate capping layer, wherein the gate dielectric layer is positioned on the fin, the gate bottom conductive layer is positioned on the gate dielectric layer, the gate top conductive layer is positioned on the gate bottom conductive layer, and the gate capping layer is positioned on the gate top conductive layer in order to “exhibit improved reliability by preventing a short or leakage current between a gate electrode disposed on an isolation insulating layer and a source/drain region.” (Shin, [0006])
Yang in view of Shin do not disclose:
and a gate capping layer,
and the gate capping layer is positioned on the gate top conductive layer.
However, Kim discloses:
and a gate capping layer (89),
and the gate capping layer (89) is positioned on the gate top conductive layer (86); ([0069], Fig. 3F)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yang, Shin and Kim to have a gate capping layer, and the gate capping layer is positioned on the gate top conductive layer in order to “prevent a defective phenomenon such as a phenomenon in which the gate line of the inclined gate structure is undesirably short-circuited with a contact disposed adjacent thereto.” (Kim, [0104])
Regarding claim 2, Yang discloses the semiconductor device of claim 1, further comprising barrier layers (105) positioned between the lower portions (101-1) and the middle portions (101-3), and on the sides of the upper portions (101-5). ([0103], Fig. 24)
Regarding claim 3, Yang discloses the semiconductor device of claim 2, further comprising barrier spacers, wherein the barrier spacers are positioned on sides and top surfaces of the barrier layers. ([0104], Fig. 24)
Regarding claim 4, Yang discloses the semiconductor device of claim 1, further comprising a first dielectric layer (501) positioned on the gate structure (200) and a second dielectric layer (503) positioned on the first dielectric layer (501), wherein the top conductive layers (107) are positioned on the upper portions (101-5). ([0063], Fig. 24)
Regarding claim 5, Yang discloses the semiconductor device of claim 4, further comprising barrier layers (105) and barrier spacers (109), wherein the barrier layers (105) are between the middle portions (101-3) and the first dielectric layer (501), and between the first dielectric layer (501) and the upper portions (101-5), and the barrier spacers (109) are positioned on sides of the barrier layers (105) and on the top surface of the second dielectric layer (503). ([0104], Fig. 24)
Regarding claim 6, Yang discloses the semiconductor device of claim 5, further comprising bottom conductive layers (111) positioned between the lower portions (101-1) and the impurity regions (301), wherein the bottom conductive layers (111) are formed of titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. ([0106], Fig. 24)
Regarding claim 7, Yang discloses the semiconductor device of claim 1, further comprising gate spacers (207) positioned on sides of the gate structures (200) and adjacent to the impurity regions (301), wherein top surfaces of the gate spacers (207) are substantially coplanar with a top surface of the gate structure (200). ([0061], Fig. 24)
Regarding claim 8, Yang discloses the semiconductor device of claim 7. Yang does not disclose wherein the gate spacer has a shoulder portion.
However, Shin discloses:
the gate spacer (60+34) has a shoulder portion (annotated below). (Fig. 4B)
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485
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It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yang and Shin for the gate spacer has a shoulder portion in order to have an “isolation insulating layer that is self-alignedly formed to separate fin regions from each other. Such devices may exhibit improved reliability by preventing a short or leakage current between a gate electrode disposed on an isolation insulating layer and a source/drain region.” (Shin, [0006])
Regarding claim 9, Shin discloses the semiconductor device of claim 8, wherein the gate dielectric layer (80c) includes a U-shaped or V-shaped cross-sectional profile (per [0128]), and the two ends of the gate dielectric layer (80c) extend in opposite directions, aligning with a top surface of the shoulder portion (annotated above). (Fig. 4B)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Shin for similar reasons mentioned beforehand.
Regarding claim 10, Shin discloses the semiconductor device of claim 9, wherein the gate bottom conductive layer (82) exhibits a cross-sectional profile that is V-shaped or U-shaped (per [0128]), and a bottom portion of the gate bottom conductive layer (82) creates a first valley; wherein both ends of the gate bottom conductive layer (82) protrude above the top surface of the shoulder portion (annotated above), and a top portion of a top surface of the gate bottom conductive layer is at a third vertical level, which is higher than the top surface of the shoulder portion. (Fig. 4B)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Shin for similar reasons mentioned beforehand.
Regarding claim 11, Shin discloses the semiconductor device of claim 10, wherein both ends of the gate top conductive layer (84) protrude above the top surface of the shoulder portion (annotated above), a top portion of a top surface of the gate top conductive layer is at a fourth vertical level, which is higher than the top surface of the shoulder portion (annotated above), and a bottom surface of the gate top conductive layer (84) is at the first vertical level, lower than the top surface of the shoulder portion. (Fig. 4B)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Shin for similar reasons mentioned beforehand.
Shin does not disclose:
wherein the gate top conductive layer exhibits a cross-sectional profile that is V-shaped or U-shaped and a bottom portion of the gate top conductive layer creates a second valley.
However, Kim discloses:
wherein the gate top conductive layer (86) exhibits a cross-sectional profile that is V-shaped or U-shaped and a bottom portion of the gate top conductive layer creates a second valley; (Fig. 3F)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Shin and Kim for similar reasons mentioned beforehand.
Regarding claim 12, Kim discloses the semiconductor device of claim 11, wherein a bottom portion of the gate capping layer (89) has a downward-pointing protrusion-shaped cross-sectional profile (PU1), wherein the bottom portion of the gate capping layer (89) is at a second vertical level lower than the top surface of the shoulder portion (annotated below). ([0069], Fig. 3F)
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496
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It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Kim for similar reasons mentioned beforehand.
Regarding claim 13, Yang discloses the semiconductor device of claim 4, wherein the middle portions (101-3) are positioned within the first dielectric layer (501), and the upper portions (101-5) are positioned within the second dielectric layer (503). (Fig. 24)
Regarding claim 14, Yang discloses the semiconductor device of claim 13, wherein a width of the lower portion (101-1) is greater than the width of the middle portions (101-3). ([0013], Fig. 24)
Regarding claim 15, Yang discloses the semiconductor device of claim 13, wherein the width of the upper portion (101-5) is greater than the width of the middle portion (101-3). ([0014], Fig. 24)
Regarding claim 16, Yang discloses the semiconductor device of claim 13, wherein the width of the upper portion (101-5) is greater than a width of the lower portion (101-1). ([0015])
Conclusion
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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