Prosecution Insights
Last updated: October 01, 2026
Application No. 18/815,693

MANUFACTURING METHOD OF ELECTRONIC PACKAGE

Non-Final OA §103
Filed
Aug 26, 2024
Priority
Feb 16, 2024 — TW 113105527
Examiner
GONZALES, VICENTE ROLANDO
Art Unit
Tech Center
Assignee
Siliconware Precision Industries Co., Ltd.
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
3 granted / 3 resolved
+40.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
18 currently pending
Career history
28
Total Applications
across all art units

Statute-Specific Performance

§103
66.2%
+26.2% vs TC avg
§102
18.8%
-21.2% vs TC avg
§112
9.8%
-30.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 3 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 1 is objected to because of the following informalities: In claim 1, line 4, “heat dissipation” should read “heat dissipation structure”. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-4 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi et al. (US Patent Pub 20070284730 A1) in view of Dani et al. (US Patent pub 20030077478 A1). Regarding Claim 1, Shi teaches a method of manufacturing an electronic package, comprising: disposing an electronic element and a heat dissipation structure on a carrier structure, wherein the heat dissipation structure is disposed on the electronic element by a conductor, and a flux material is sandwiched between the conductor and the heat dissipation structure and between the conductor and the electronic element (Shi, fig. 1 teaches disposing an electronic element 130 and a heat dissipation 120 on a carrier substrate 240 (see fig. 2). Heat dissipation 120 is disposed on the electronic element 130 by conductor 110. Fig. 1 and paragraphs 0019 and 0020 teach flux material 172 sandwiched between conductor 110 and the heat dissipation structure 120 and flux material 171 sandwiched between the conductor 110 and the electronic element 130); and performing a first heating operation at a first temperature to vaporize the flux material as well as melt the conductor, and forming inter-metallic compound layers between the heat conductor and the heat dissipation structure and between the heat conductor and the electronic element (Shi, paragraph 0042 teaches performing a first heating operation 330 wherein the flux is vaporized. Further, paragraph 0044 teaches the heating operation 330 takes place at a first temperature, which is about the melting point of the materials of the thermal interface (conductor), which when melted would form inter-metallic compound layers (see paragraph 0029) between the heat conductor 210, the heat dissipation structure 220, and the electronic element 230). Shi fails to teach utilizing two separate heating operations to vaporize the flux and melt the conductor. However, Dani teaches a method of making an electronic assembly wherein first and second heating operations are performed at first and second temperatures, and wherein the second heating operation at a second temperature is used to melt the conductor (Dani, fig. 4 teaches a thermal cycle having a first heating operation (the first heating operation is interpreted as the ramping of the temperature to 125 degrees Celsius) and second heating operations at first and second temperatures (125 and 170 degrees Celsius, respectively), wherein the second temperature (170 degrees Celsius) melts the conductor (see paragraph 0030)). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Dani into the method of Shi by forming the method of making an electronic assembly having two heating operations having first and second temperatures, wherein a second heating operation at a second temperature to melt the conductor. The ordinary artisan would have been motivated to modify Shi in the manner set forth above for at least the purpose of lowering the temperature during the thermal cycle such that the materials that the conductor is composed of can cure and solidify at selected temperatures (Dani, paragraph 0023). Regarding Claim 2, Shi in view of Dani teaches the method of claim 1, wherein the conductor is a thermal interface material layer (Shi, paragraph 0023 teaches the conductor 210 (represented as 110 in fig. 1) is a thermal interface). Regarding Claim 3, Shi in view of Dani teaches the method of claim 2, wherein a material of the thermal interface material layer is metal indium or indium silver alloy (Shi, fig. 1 and paragraph 0015 teaches the thermal interface material layer 110 is formed of an indium silver alloy). Regarding Claim 4, Shi in view of Dani teaches the method of claim 1, wherein the second temperature is higher than the first temperature (Dani, fig. 4 teaches second temperature 170 degrees Celsius is higher than first temperature 125 degrees Celsius). Regarding Claim 13, Shi in view of Dani teaches the method of claim 1, wherein a material of the heat dissipation structure is metal copper (Shi, fig. 2 and paragraph 0024 teaches heat dissipation structure 220 includes copper). Regarding Claim 14, Shi in view of Dani teaches the method of claim 1, wherein an inactive surface of the electronic element can be plated with an interface metal layer, and the interface metal layer is a stacked multi-layer metal layer (Shi, fig. 2 and paragraph 0025 teaches the inactive surface of electronic element 230 is the backside 252. Fig. 2 and paragraph 0026 teaches 252 can be plated with a stacked multi-layer metal layer 236). Claim(s) 5-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi in view of Dani as applied to claims 1-4 and 13-14 above, and further in view of Hsueh et al. (US Patent Pub 20230386964 A1). Regarding Claim 5, Shi in view of Dani teaches the method of claim 4, wherein two temperature operations are performed to vaporize the flux material and melt the conductor, and the second temperature is higher than the first temperature. Shi in view of Dani fail to specifically teach the method wherein the first temperature is higher than a boiling point of the flux material, and lower than a melting temperature of the conductor. However, Hsueh teaches a method of forming an electronic assembly wherein the flux material having a boiling point such that the first temperature is higher than a boiling point of the flux material, and lower than a melting temperature of the conductor (Hsueh, paragraph 0014 teaches that the flux material may be formed of lactic acid. Applicant’s own specification (paragraph 0034) teaches the boiling point of lactic acid is 122 degrees Celsius, which is within the boiling point range such that the first temperature is higher than a boiling point of the flux material, and lower than a melting temperature of the conductor). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Hsueh into the method of Shi in view of Dani by utilizing a method wherein the first temperature is higher than a boiling point of the flux material, and lower than a melting temperature of the conductor. The ordinary artisan would have been motivated to modify Shi in view of Dani in the manner set forth above for at least the purpose removing impurities and oxides from the surfaces of the chips (Hsueh, paragraph 0015). Regarding Claim 6, Shi in view of Dani and in further view of Hsueh teaches the method of claim 4, wherein the second temperature is higher than a melting temperature of the conductor (Dani, fig. 4 teaches second temperature 170 degrees Celsius is higher than a melting temperature (157 degrees Celsius) of the conductor). Regarding Claim 7, Shi in view of Dani teach the method of claim 1. Shi in view of Dani fail to teach the method wherein the flux material includes a monocarboxylic acid. However, Hsueh teaches a method of forming a stacked electronic chip assembly wherein the flux material includes monocarboxylic acid (Hsueh, paragraph 0014 teaches the flux can be formed of lactic acid, which Applicant’s own specification (paragraph 0013) teaches is a monocarboxylic acid). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Hsueh into the method of Shi in view of Dani by utilizing a method wherein the flux material includes a monocarboxylic acid. The ordinary artisan would have been motivated to modify Shi in view of Dani in the manner set forth above for at least the purpose removing impurities and oxides from the surfaces of the chips (Hsueh, paragraph 0015). Regarding claim 8, Shi in view of Dani and in further view of Hsueh teaches the method of claim 7, wherein the monocarboxylic acid is formic acid, glycolic acid, glacial acetic acid, lactic acid, or a combination thereof (Hsueh, paragraph 0014 teaches the flux can be formed of lactic acid). Regarding Claim 9, Shi in view of Dani and in further view of Hsueh teaches the method of claim 7, wherein the monocarboxylic acid is diluted with a low boiling point solvent (Hsueh, paragraph 0014 teaches the lactic acid flux is diluted with isopropyl alcohol, which Applicant’s own specification (paragraph 0015) teaches is a low boiling point solvent). Regarding Claim 10, Shi in view of Dani and in further view of Hsueh teaches the method of claim 9, wherein the low boiling point solvent is isopropyl alcohol (Hsueh, paragraph 0014 teaches the lactic acid flux is diluted with isopropyl alcohol). Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi in view of Dani as applied to claims 1-4 and 13-14 above, and further in view of Hua et al. (US Patent Pub 20050280142 A1). Regarding Claim 11, Shi in view of Dani teaches the method of claim 1. Shi in view of Dani fail to teach a method wherein an outer surface of the heat dissipation structure is disposed with a metal anti-oxidation layer. However, Hua teaches a method of forming an electronic assembly wherein an outer surface of the heat dissipation structure is disposed with a metal anti-oxidation layer (Hua, fig. 1 and paragraph 0012 teaches the heat dissipation structure 20 has an outer surface 22 formed of a nickel metal anti-oxidation layer. Paragraph 0017 of Applicant’s own specification teaches nickel can be used as a metal anti-oxidation layer). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Hua into the method of Shi in view of Dani by utilizing a method wherein an outer surface of the heat dissipation structure is disposed with a metal anti-oxidation layer. The ordinary artisan would have been motivated to modify Shi in view of Dani in the manner set forth above for at least the purpose of utilizing the nickel metal anti-oxidation layer as a protective layer and diffusion barrier (Hua, paragraph 0012). Regarding Claim 12, Shi in view of Dani and further in view of Hua teaches the method of claim 11, wherein the material of the metal anti-oxidation layer is metal nickel (Hua, fig. 1 and paragraph 0012 teaches the heat dissipation structure 20 has an outer surface 22 formed of a nickel metal anti-oxidation layer.) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICENTE R GONZALES whose telephone number is (571)272-3365. The examiner can normally be reached Monday - Friday 7:30 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /V.R.G./Examiner, Art Unit 2899 /JOHN M PARKER/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Aug 26, 2024
Application Filed
Aug 25, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740486
ELECTRONIC DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS AND METHOD OF MANUFACTURING THE SAME
2y 11m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 9m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 3 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month