DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for, in brief and saliently: a pair of far banks coupled to a first pair of local bitlines, a pair of near banks coupled to a second pair of local bitlines, a far global bit line coupled to the first pair of local bitlines, does not reasonably provide enablement for “a first NAND gate having a first input coupled to the second pair of local bitlines and a second input coupled to the far global bit line; a near global bit line coupled to the output of the first NAND gate.”
The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention commensurate in scope with these claims. FIG. 3 of the drawings and [0020] in the specification seem relevant. [0020] discloses “The multi-bank SRAM 300 further comprises a NOR gate 380 having a first input coupled to the output of the near bank NAND gate 360, a second input coupled to the far global bitline, and an output which couples the near global bit line to the global I/O circuit 370.” At least [0020] of the specification and FIG. 3 clearly define the meaning of “coupled.” In the context of the specification, as set forth in at least [0020] and FIG. 3, “coupled” is defined as directly connected. An input of 380 is coupled (directly connected) to the output of NAND gate 360, and a second input of 380 coupled (directly connected) to the far global bitline (GBL Far). It is not apparent from the disclosure as set forth in the specification and drawings that, as claimed, “a first NAND gate having a first input coupled to the second pair of local bitlines and a second input coupled to the far global bit line.” The claimed second pair of local bitlines, as the claim requires, is found in the “Near Bank” 350 in FIG. 3. This second pair of local bitlines are the inputs to NAND gate 360. And the output of NAND gate 360 is coupled (directly connected) to an input of NOR gate 380. This analysis is in agreement with the disclosure in at least [0020] of the specification.
Moreover, the claim limitation of “a near global bit line coupled to the output of the first NAND gate,” is also in complete disagreement with the disclosure as set forth in at least [0020] of the specification and FIG. 3 of the drawings. In fact, near global bitline (GBL Near) is coupled (directly connected) to the output of NOR gate 380.
It is, therefore, unambiguously clear that what is claimed in claim 1 is in disagreement with the disclosure as set forth in at least [0020] of the specification and FIG. 3 of the drawings.
Claim(s) 2-7 depend from claim 1, and as such are also rejected for at least the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20200402575.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827