Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parikh et al. (US Patent No. 8,878,245), hereinafter referred to as Parikh, in view of Prechtl et al. (Pub. No. US 20160240645 A1), hereinafter referred to as Prechtl, and in view of Beach et al. (US Patent No. 7,728,355 B2).
Regarding claim 1, Parikh teaches a high electron mobility transistor (HEMT), comprising: a substrate (Fig. 1a, substrate 102; Col. 4, lines 7-11); a barrier layer (Fig. 1b, barrier layer 106; Col. 4, lines 25-44); a hard mask on the barrier layer (Fig. 1c, regrowth mask 108; Col. 4, lines 25-44); and a source electrode and a drain electrode adjacent to two sides of the gate electrode (Fig. 1h, source contact 116, drain contact 114, gate contact 120; Col. 5, lines 7-22). However, Parikh does not explicitly teach a buffer layer on a substrate, a barrier layer on the buffer layer; a p-type semiconductor layer on the barrier layer, wherein the p-type semiconductor layer comprises a L-shape and the p-type semiconductor layer comprises: a first portion on the barrier layer; and a second portion on the hard mask; and a gate electrode on the p-type semiconductor layer.
Prechtl teaches a p-type semiconductor layer on the barrier layer, wherein the p-type semiconductor layer comprises a L-shape and the p-type semiconductor layer comprises: a first portion on the barrier layer (Fig. 8, p-type doped GaN layer 94, AlGaN barrier layer 32, second recess portion 93; ¶75-76); and a second portion (Fig. 8, p-type doped GaN layer 94, first recess portion 91; ¶75-76); and a gate electrode on the p-type semiconductor layer (Fig. 8, gate electrode 25, upper surface 95; ¶75-76).
Parikh and Prechtl are analogous art as they are in the same field of endeavor of High Electron Mobility Transistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the gate contact of Parikh with the teachings of Prechtl such that there is a p-type semiconductor layer on the barrier layer, wherein the p-type semiconductor layer comprises a L-shape and the p-type semiconductor layer comprises: a first portion on the barrier layer; and a second portion on the hard mask; and a gate electrode on the p-type semiconductor layer. For the purpose of having a p-type GaN Gate-Injection Transistor, which can reduce the energy consumption in power conversion systems and can be used as a normally off transistor device, as recognized by Prechtl.
However, Parikh in view of Prechtl still does not explicitly teach a buffer layer on a substrate, and a barrier layer on the buffer layer. Beach teaches a buffer layer on a substrate (Fig. 1, substrate 38, buffer layer 14; Col. 2, line 60 – Col. 3, line 30), and a barrier layer on the buffer layer (Fig. 1, barrier layer 28, buffer layer 14; Col. 2, line 60 – Col. 3, line 30).
Parikh, Prechtl, and Beach are analogous art as they are in the same field of endeavor of High Electron Mobility Transistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Parikh in view of Prechtl with the teachings of Beach such that there is a buffer layer on a substrate; a barrier layer on the buffer layer; and a source electrode and a drain electrode adjacent to two sides of the gate electrode on the buffer layer. For the purpose of including a buffer layer in the device which can have benefits such as reducing stress and/or strain, better thermal performance, and reducing current leakage.
Regarding claim 2, Parikh further teaches the hard mask is around the gate electrode (Fig. 1h, regrowth mask residual layer 110, gate contact 120; Col. 5, lines 13-22). However, Parikh does not explicitly teach the hard mask is around the p-type semiconductor layer.
Prechtl teaches a p-type semiconductor layer with a gate electrode on top (Fig. 8, p-type doped GaN layer 94, gate electrode 25, upper surface 95; ¶75-76).
Parikh and Prechtl are analogous art as they are in the same field of endeavor of High Electron Mobility Transistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the gate structure of Parikh with the teachings of Prechtl such that the hard mask is around the p-type semiconductor layer and the gate electrode. For the purpose of having a p-type GaN Gate-Injection Transistor, which can reduce the energy consumption in power conversion systems and can be used as a normally off transistor device, as recognized by Prechtl. Also, to have the mask layer function as a passivation layer and/or spacer in the final device, as recognized by Parikh.
Regarding claim 3, Parikh further teaches the hard mask is under the gate electrode (Fig. 1h, regrowth mask residual layer 110, gate contact 120; Col. 5, lines 13-22). However, Parikh does not explicitly teach the hard mask is under the p-type semiconductor layer.
Prechtl teaches a p-type semiconductor layer with a gate electrode on top (Fig. 8, p-type doped GaN layer 94, gate electrode 25, upper surface 95; ¶75-76).
Parikh and Prechtl are analogous art as they are in the same field of endeavor of High Electron Mobility Transistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the gate structure of Parikh with the teachings of Prechtl such that the hard mask is under the p-type semiconductor layer. For the purpose of having a p-type GaN Gate-Injection Transistor, which can reduce the energy consumption in power conversion systems and can be used as a normally off transistor device, as recognized by Prechtl. Also, to have the mask layer function as a passivation layer and/or spacer in the final device, as recognized by Parikh.
Regarding claim 4, Parikh does not explicitly teach the first portion is connected to the second portion directly.
Prechtl teaches the first portion is connected to the second portion directly (Fig. 8, p-type doped GaN layer 94, AlGaN barrier layer 32, first recess portion 91, second recess portion 93; ¶75-76).
Parikh and Prechtl are analogous art as they are in the same field of endeavor of High Electron Mobility Transistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Parikh with the teachings of Prechtl such that the first portion is connected to the second portion directly. For the purpose of having a p-type GaN Gate-Injection Transistor, which can reduce the energy consumption in power conversion systems and can be used as a normally off transistor device, as recognized by Prechtl.
Regarding claim 5, Parikh does not explicitly teach the p-type semiconductor layer comprises p-type gallium nitride (pGaN).
Prechtl teaches the p-type semiconductor layer comprises p-type gallium nitride (pGaN) (Fig. 8, p-type doped GaN layer 94; ¶75-76).
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Parikh with the teachings of Prechtl such that the p-type semiconductor layer comprises p-type gallium nitride (pGaN). For the purpose of having a p-type GaN Gate-Injection Transistor, which can reduce the energy consumption in power conversion systems and can be used as a normally off transistor device, as recognized by Prechtl.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hsu et al. (US Patent No. 9,379,191), Bito (US Patent No. 7,456,444), and Cheng (Pub. No. CN 104051522 B).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./Examiner, Art Unit 2897
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