Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/816,164 filed on August 27, 2024.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “SEMICONDUCTOR DEVICE WITH MULTI-LAYERED ISOLATION STRUCTURE .
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1, 6-10 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lu (2022/0157824 A1).
Regarding independent claim 1, Lu teaches a semiconductor device (10, Fig. 1), comprising:
a substrate (110, para [0041]);
at least one isolation feature (130, para [0041]) disposed in the substrate (100), wherein the at least one isolation feature (130) defines a plurality of active regions (104, para [0041]);
a storage capacitor (20, para [0038]) disposed over the substrate (100);
an access transistor (30, para [0038]) comprising a plurality of impurity regions (340, para [0042]) disposed in the active region (104); and
a conductive feature (50, para [0039]) extending from the storage capacitor (20) into the substrate (110) for electrically coupling the storage capacitor (20) to the access transistor (30).
Regarding claim 6, Lu teaches wherein (Fig. 1), the conductive feature (50) comprises a lower portion (510, para [0046]) in the substrate (110) and an upper portion (520, para [0046]) interposed between the substrate (110) and the storage capacitor (20), wherein the lower portion (510) has a first critical dimension (CD1, para [0046]), and the upper portion (520) has a second critical dimension (CD2, para [0046]) greater than the first critical dimension (CD1).
Regarding claim 7, Lu teaches wherein (Fig. 1), the first critical dimension (CD1) of the lower portion (510) of the conductive feature (50) gradually decreases (see Fig. 1) at positions of increasing distance from the upper portion (520).
Regarding claim 8, Lu teaches wherein (Fig. 1), the access transistor (30) further comprises:
a word line (322, para [0042]) disposed in the substrate (110) and across the active regions (104), wherein the impurity regions (340) are disposed on either side of the word line (322); and
an insulative liner (312, para [0042]) sandwiched between the substrate (110) and the word line (322).
Regarding claim 9, Lu teaches wherein (Fig. 1), further comprising:
a dielectric layer (40, para [0039]) between the storage capacitor (20) and the substrate (110) to encapsulate the access transistor (30) and enclose the conductive feature (50);
a bit line (44, para [0038]) buried in the dielectric layer (40); and
a conductive plug (42, para [0039]) extending from the bit line (44) into the substrate (110) for electrically coupling the bit line (44) to the access transistor (30).
Regarding claim 10, Lu teaches wherein (Fig. 1), the storage capacitor (20) comprises:
a plurality of storage nodes (210, para [0040]) respectively contacting the conductive features (50);
a capacitor insulator (220, para [0040]) encapsulating the storage nodes (210); and
a top electrode (230, para [0040]) disposed on the capacitor insulator (220).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
12. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
13. Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (2022/0157824 A1) as applied to claim 1 above, and further in view of KIM (US 2011/0260238 A1).
Regarding claim 2, Lu teaches all of the limitations of claim 1 from which this claim depends.
Lu is explicitly silent of disclosing wherein, each of the at least one isolation features comprises:
a first filling layer filling a trench disposed in the substrate;
a second filling layer disposed within the first filling layer; and
a liner layer lining an inner surface of the trench and surrounding the first filling layer.
KIM teaches wherein (Fig. 2L), each of the at least one isolation features (104, para [0042]) comprises:
a first filling layer (104b, para [0047]) filling a trench (T, para [0046]) disposed in the substrate (100);
a second filling layer (104c) disposed within the first filling layer (104b); and
a liner layer (104a) lining an inner surface of the trench (T) and surrounding the first filling layer (104b).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by KIM, and substitute the isolation features of Lu, w/multi layered isolation film, in order to reduce or block the thermal transfer, and to prevent failures or component cracking.
Regarding claim 3, Lu and KIM teach all of the limitations of claim 2 from which this claim depends.
Lu is explicitly silent of disclosing wherein, the first filling layer and the liner layer comprise a U-shaped cross-sectional profile.
KIM teaches wherein (Fig. 2L), the first filling layer (104b) and the liner layer (104a) comprise a U-shaped cross-sectional profile (see Fig. 2L).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by KIM, and substitute the isolation features of Lu, w/U-shaped multi layered isolation film, in order to provide high-capacity energy dissipation, block the thermal transfer, and to prevent failures or component cracking.
Regarding claim 4, Lu and KIM teach all of the limitations of claim 2 from which this claim depends.
KIM teaches wherein (see Fig. 2L), a top surface of the first filling layer (104b), a top surface of the second filling layer (104c) and a top surface of the liner layer (104a) are coplanar (i.e. flat surface).
Regarding claim 5, Lu and KIM teach all of the limitations of claim 4 from which this claim depends.
KIM teaches wherein (see Fig. 2L), a bottom surface of the second filling layer (104c) is at a vertical level higher than a bottom surface of the first filling layer (104b).
Examiner’s Note
14. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
16. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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