DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1, 3-7, and 9-12 are rejected under 35 U.S.C. 103 as obvious over Yoshino (US 2009/0129037 A1), hereinafter as Y1, in view of Nakamura (JP 2002171052 A, see attached translation document), hereinafter as N1
4. Regarding Claim 1, Y1 discloses an electronic package (see in particular Figs. 7(a)-(e), 8(g)), comprising:
an encapsulating structure (see Fig. 7(a)-(e), 8(g), elements 500, 506 and see [0096-0097, 0101, 0082] the two material can be selected to be the same) having a first surface (first lower surface) and a second surface (second upper surface) opposing to each other, and provided with a recess (recess at a boundary with element 508 see Fig. 7(g)) on the second surface and a plurality of vias (vias of element 511, see [0102]) connecting the first surface to the second surface, wherein a plurality of openings (see Fig. 7(b)-(e) openings of element 503) connected to the first surface are formed on a bottom surface of the recess, such that the recess combines with the plurality of openings to connect the first surface to the second surface (see Fig. 8(g));
a circuit structure (bottom elements 510, 513 and embedded conductive elements) disposed on the first surface of the encapsulating structure, and exposed from the plurality of openings and the plurality of vias (see Fig. 8(g));
a plurality of conductive pillars (conductive pillars plated in the via elements 511, see [0102]) disposed in the plurality of vias and electrically connected to the circuit structure (see Fig. 8(g) and [0102]);
an electronic component (element 502, see [0096]) disposed in the recess and electrically connected to the circuit structure (see Fig. 8(g)); and
a routing structure (top elements 510, 513 and embedded conductive elements) disposed on the second surface of the encapsulating structure and electrically connected to the plurality of conductive pillars and/or the electronic component (see Fig. 8(g)).
Y1 does not explicitly disclose the openings are concaves.
N1 discloses the openings are concaves (see Fig. 5 concave openings of element 3 with the solder bump element 8 (9) embedded and [0031] “openings 3a and 3b whose side surfaces are concave with a roundness R2”).
The shape of the opening as taught by N1 is incorporated as the shape of the openings of Y1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of N1 with Y1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known openings shape for embedded solder bumps for another in a similar device for which different opening shapes are provided as alternatively selectable (see N1 Figs. 3-7).
5. Regarding Claim 3, Y1, N1 disclose the electronic package of claim 1, wherein (see Y1) an insulating material (element 508, see [0101]) is filled between the electronic component and the recess (see Fig. 8(g)).
6. Regarding Claim 4, Y1, N1 disclose the electronic package of claim 1, wherein (see Y1) the electronic component has an active surface (bottom surface) and a non-active surface (top surface) opposing to each other, and is electrically connected to the circuit structure through a plurality of conductive bumps (elements 504, see [0098]) with its active surface, wherein the plurality of conductive bumps are disposed in the plurality of concaves (see Fig. 8(g)), and there is no colloid between the non-active surface and the routing structure (see Fig. 8(g) the top surface of element 502 is in direct contact with element 510 such that there is no colloid between).
7. Regarding Claim 5, Y1, N1 disclose the electronic package of claim 4, wherein (see Y1) the non-active surface is in contact with the routing structure (see Fig. 8(g)).
8. Regarding Claim 6, Y1, N1 disclose the electronic package of claim 1, wherein (see Y1) a plurality of conductive elements (elements 516, see [0103]) are formed on a surface of the circuit structure that is not in contact with the encapsulating structure (see Fig. 8(g)).
9. Regarding Claim 7, Y1 discloses a manufacturing method of an electronic package (see in particular Figs. 7(a)-(e), 8(a)-(g)), comprising:
providing an encapsulating structure (see Fig. 7(a)-(e), 8(g), elements 500, 506 and see [0096-0097, 0101, 0082] the two material can be selected to be the same) having a first surface (first lower surface) and a second surface (second upper surface) opposing to each other, wherein the second surface of the encapsulating structure has a recess (recess at a boundary with element 508 see Fig. 7(g));
forming a circuit structure (bottom elements 510, 513 and embedded conductive elements) on the first surface of the encapsulating structure (see Fig. 8(g));
forming a plurality of vias (vias of element 511, see [0102]) on the second surface of the encapsulating structure that connect the first surface to the second surface (see Fig. 8(g)), and forming a plurality of openings (see Fig. 7(b)-(e) concaves of element 503) on a bottom surface of the recess (see Fig. 8(g));
forming a plurality of conductive pillars (conductive pillars plated in the via elements 511, see [0102]) in the plurality of vias that are connected to the circuit structure electrically (see Fig. 8(g) and [0102]), and disposing an electronic component (element 502, see [0096]) in the recess, wherein the electronic component is electrically connected to the circuit structure (see Fig. 8(g)); and
forming a routing structure (top elements 510, 513 and embedded conductive elements) on the second surface of the encapsulating structure, wherein the routing structure is electrically connected to the plurality of conductive pillars (see Fig. 8(g)).
Y1 does not explicitly disclose the openings are concaves.
N1 discloses the openings are concaves (see Fig. 5 concave openings of element 3 with the solder bump element 8 (9) embedded and [0031] “openings 3a and 3b whose side surfaces are concave with a roundness R2”).
The shape of the opening as taught by N1 is incorporated as the shape of the openings of Y1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of N1 with Y1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known openings shape for embedded solder bumps for another in a similar device for which different opening shapes are provided as alternatively selectable (see N1 Figs. 3-7).
10. Regarding Claim 9, Y1, N1 disclose the method of claim 7, wherein (see Y1) an insulating material (element 508, see [0101]) is filled between the electronic component and the recess (see Fig. 8(g)).
11. Regarding Claim 10, Y1, N1 disclose the method of claim 7, wherein (see Y1) the electronic component has an active surface (bottom surface) and a non-active surface (top surface) opposing to each other, and is electrically connected to the circuit structure through a plurality of conductive bumps (elements 504, see [0098]) with its active surface, wherein the plurality of conductive bumps are disposed in the plurality of concaves (see Fig. 8(g)), and there is no colloid between the non-active surface and the routing structure (see Fig. 8(g) the top surface of element 502 is in direct contact with element 510 such that there is no colloid between).
12. Regarding Claim 11, Y1, N1 disclose the method of claim 10, wherein (see Y1) the non-active surface is in contact with the routing structure (see Fig. 8(g)).
13. Regarding Claim 12, Y1, N1 disclose the method of claim 7, wherein (see Y1) a plurality of conductive elements (elements 516, see [0103]) are formed on a surface of the circuit structure that is not in contact with the encapsulating structure (see Fig. 8(g)).
14. Claims 2 and 8 are rejected under 35 U.S.C. 103 as obvious over Yoshino (US 2009/0129037 A1), hereinafter as Y1, in view of Nakamura (JP 2002171052 A, see attached translation document), hereinafter as N1, in view of Ogura et al. (US 2022/0230948 A1), hereinafter as O1
15. Regarding Claim 2, Y1, N1 disclose the electronic package of claim 1.
Y1, N1 do not explicitly disclose wherein the encapsulating structure is a plate body of semiconductor material.
O1 discloses wherein the encapsulating structure is a plate body of semiconductor material (see [0099] “the core panel 106 can comprise glass … silicon-like RDL wiring”; note, the material disclosed by O1 is the same material as the Applicant’s invention).
The glass material as taught by O1 is incorporated as a material of the encapsulating structure of Y1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of O1 because the combination allows for high-dimensional stability of glass enables high-density, silicon-like RDL wiring and BEOL-like I/Os even on large panels, thus increasing the productivity not possible in mold-compound based fan-out, CTE can be tailored, provides high resistivity, excellent moisture resistance, and high surface smoothness as compared to molding compounds (see O1 [0099]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known dielectric material for another in a similar device to obtain predictable results (see Y1 [0096-0097, 0101, 0082] The material of the encapsulating structure may be an epoxy or build-up and see O1 [0098-0099] material of the encapsulating structure is provided as an alternative of epoxy-mold based material).
16. Regarding Claim 8, Y1, N1 disclose the method of claim 7.
Y1, N1 do not explicitly disclose wherein the encapsulating structure is a plate body of semiconductor material.
O1 discloses wherein the encapsulating structure is a plate body of semiconductor material (see [0099] “the core panel 106 can comprise glass … silicon-like RDL wiring”; note, the material disclosed by O1 is the same material as the Applicant’s invention).
The glass material as taught by O1 is incorporated as a material of the encapsulating structure of Y1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of O1 because the combination allows for high-dimensional stability of glass enables high-density, silicon-like RDL wiring and BEOL-like I/Os even on large panels, thus increasing the productivity not possible in mold-compound based fan-out, CTE can be tailored, provides high resistivity, excellent moisture resistance, and high surface smoothness as compared to molding compounds (see O1 [0099]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known dielectric material for another in a similar device to obtain predictable results (see Y1 [0096-0097, 0101, 0082] The material of the encapsulating structure may be an epoxy or build-up and see O1 [0098-0099] material of the encapsulating structure is provided as an alternative of epoxy-mold based material).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Primary Examiner, Art Unit 2818
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