DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-6, 10, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0290866 to Hong et al. (hereinafter Hong).
With respect to claim 1, Hong discloses a method (e.g., forming a backside contact structure in a semiconductor device) (Hong, Figs. 2, 3A-3G, ¶0002, ¶0019-¶0025, ¶0054-¶0090) comprising:
forming a transistor (201) (Hong, Figs. 2, 3A, ¶0055, ¶0058-¶0059) over a semiconductor substrate (226/250), the forming the transistor (201) comprising:
forming a source/drain region (e.g., 216b/211, epitaxy 211 is formed on the epi 216B to form epitaxy recess including a portion 202 of the back side contact BSCA) (Hong, Figs. 2, 3A, ¶0071, ¶0075) through an epitaxy process;
performing a backside thinning process (e.g., removing SiGe layer 250 of the substrate 226/250) (Hong, Figs. 2, 3C, ¶0072) to thin the semiconductor substrate (226/250);
etching the semiconductor substrate (226) (Hong, Figs. 2, 3D, ¶0075) to form a contact opening (e.g., epitaxy recess), wherein a back surface of the source/drain region (216b) is exposed through the contact opening;
performing an amorphization implantation process (Hong, Figs. 2, 3E, ¶0076) through the contact opening (e.g., epitaxy recess) to generate an amorphous region (e.g., amorphous epi) in the source/drain region; and
forming a silicide region (e.g., silicide region 272) (Hong, Figs. 2, 3F-3G, ¶0077-¶0079) on the source/drain region.
Regarding claim 2, Hong discloses the method of claim 1. Further, Hong discloses the method further comprising an anneal process to recrystallize the amorphous region (Hong, Figs. 2, 3E, ¶0076).
Regarding claim 5, Hong discloses the method of claim 2. Further, Hong discloses the method, wherein the silicide region (e.g., silicide region 272) (Hong, Figs. 2, 3G, ¶0078) is formed after the anneal process in an additional anneal process separate from the anneal process (e.g., laser anneal to form recrystallization epi in Fig. 3E is different from a laser annealing step to form a silicide region in Fig. 3G).
Regarding claim 6, Hong discloses the method of claim 1. Further, Hong discloses the method further comprising performing a doping implantation process (e.g., ion implantation and doping process, and doping activation process in Fig. 3E) (Hong, Figs. 2, 3E, ¶0077) on the source/drain region, wherein the doping implantation process is performed through the contact opening.
Regarding claim 10, Hong discloses the method of claim 1. Further, Hong discloses the method further comprising etching a dielectric layer (e.g., dry etching on the substrate to form backside contact includes etching the BDI 224 made of dielectric material) (Hong, Figs. 2, 3A, 3D, ¶0020, ¶0055, ¶0070, ¶0075) that separates the semiconductor substrate (226) from the source/drain region (216b) to extend the contact opening (202/204) to the source/drain region (261b).
With respect to claim 18, Hong discloses a method (e.g., forming backside contact structure in a semiconductor device) (Hong, Figs. 2, 3A-3G, ¶0002, ¶0019-¶0025, ¶0054-¶0090) comprising:
forming a transistor (201) (Hong, Figs. 2, 3A, ¶0055, ¶0058-¶0059) over a semiconductor substrate (226/250), the forming the transistor (201) comprising:
forming a plurality of semiconductor nanostructures (e.g., channel structures 220 of the nanosheet transistor 201) (Hong, Figs. 2, 3A, ¶0059) over the semiconductor substrate (226); and
performing an epitaxy process (e.g., 216b/211, epitaxy 211 is formed on the epi 216B to form epitaxy recess including a portion 202 of the back side contact BSCA) (Hong, Figs. 2, 3A, ¶0071, ¶0075) to form an epitaxy region (216b/211) connected to the plurality of semiconductor nanostructures (220);
forming a contact opening (e.g., 202/204 including an epitaxy recess 202) (Hong, Figs. 2, 3D, ¶0075) from a backside of the semiconductor substrate to reveal the epitaxy region (216b);
performing an amorphization implantation process (Hong, Figs. 2, 3E, ¶0076) on the epitaxy region (216b) to form an amorphous region (e.g., amorphous epi);
performing a first anneal process (e.g., a first anneal to crystalize epi) (Hong, Figs. 2, 3E, ¶0077) to partially anneal the amorphous region; and
forming a silicide region (e.g., forming a silicide region 272 by a laser annealing step) (Hong, Figs. 2, 3F-3G, ¶0077-¶0079) based on a part (e.g., crystalized epi) of the epitaxy region (216b) that is implanted by the amorphization implantation process.
Regarding claim 19, Hong discloses the method of claim 18. Further, Hong discloses the method further comprising performing a second anneal process (e.g., a laser annealing step to form a silicide region 272 in Fig. 3G) (Hong, Figs. 2, 3F-3G, ¶0077-¶0079) during the forming the silicide region, wherein the first anneal process and the second anneal process are separate anneal processes (e.g., a laser annealing step to form a silicide region 272 in Fig. 3G is different from a laser anneal to form recrystallization epi in Fig. 3E).
Regarding claim 20, Hong discloses the method of claim 18. Further, Hong discloses the method, further comprising forming a contact plug (e.g., depositing a metal layer to form back side contact (BSCA) 210) (Hong, Figs. 2, 3H, ¶0080) in the contact opening.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-6, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0012147 to Chu et al. (hereinafter Chu) in view of Hong (US 2024/0290866).
With respect to claims 1 and 2, Chu discloses a method (e.g., forming backside contact structure in a semiconductor device) (Chu, Figs. 2A-2D, 4-10, 14-15, ¶0001, ¶0016-¶0020, ¶0044-¶0074) comprising:
forming a transistor (e.g., FETs 102A/102B) (Chu, Figs. 2A-2B, 4-6, ¶0022-¶0031, ¶0047-¶0050) over a semiconductor substrate (406), the forming the transistor (102A/102B) comprising:
forming a source/drain region (e.g., 110A/110B) (Chu, Figs. 2A-2B, 4-6, ¶0027-¶0028, ¶0050) through an epitaxy process;
performing a backside thinning process (e.g., a substrate polishing process includes a thinning process of the substrate 406) (Chu, Figs. 8A, 8B, ¶0052) to thin the semiconductor substrate (406);
etching the semiconductor substrate (406) (Chu, Figs. 10, 14, ¶0054, ¶0064) to form a contact opening (e.g., 1064A/1064B), wherein a back surface of the source/drain region (110A/110B) is exposed through the contact opening (1064A/1064B); and
forming a silicide region (e.g., 148B-2/148B-1) (Chu, Figs. 14, 15, ¶0065-¶0072) on the source/drain region (110A/110B).
Further, Chu does not specifically disclose the method comprising; performing an amorphization implantation process through the contact opening to generate an amorphous region in the source/drain region (as claimed in claim 1); further comprising an anneal process to recrystallize the amorphous region (as claimed in claim 2); wherein the silicide region is formed after the anneal process in an additional anneal process separate from the anneal process (as claimed in claim 5).
However, Hong teaches a method of forming a backside contact structure in a semiconductor device (Hong, Figs. 2, 3A-3G, ¶0002, ¶0019-¶0025, ¶0054-¶0090) comprising performing an amorphization implantation process (Hong, Figs. 2, 3E, ¶0076) by using an implantation to generate an amorphous region in the epitaxy recess of the source/drain region, and recrystallization epi by using a laser anneal process, wherein the silicide region (e.g., silicide region 272 is formed in Fig. 3G after the anneal in Fig. 3E) (Hong, Figs. 2, 3F-3G, ¶0077-¶0079) is formed after the anneal process (Hong, Fig. 3E, ¶0077) in an additional anneal process separate from the anneal process, to make a good silicide in the subsequent steps to achieve low contact resistance (Hong, ¶0075-¶0077).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chu by performing amorphization epi and recrystallization epi processes using ion implantation and anneal process in the epitaxy recess of the source/drain region as taught by Hong to have the method comprising: an amorphization implantation process through the contact opening to generate an amorphous region in the source/drain region (as claimed in claim 1); further comprising an anneal process to recrystallize the amorphous region (as claimed in claim 2); wherein the silicide region is formed after the anneal process in an additional anneal process separate from the anneal process (as claimed in claim 5), to make a good silicide in the subsequent steps to achieve low contact resistance (Hong, ¶0075-¶0077).
Regarding claim 6, Chu in view of Hong discloses the method of claim 1. Further, Chu does not specifically disclose the method further comprising performing a doping implantation process on the source/drain region, wherein the doping implantation process is performed through the contact opening. However, Hong teaches the method further comprising performing ion implantation and a doping process (Hong, Fig. 3E, ¶0077) on the source/drain epi region having the epitaxy recess, to achieve low contact resistance.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chu/Hong by performing amorphization epi and recrystallization epi processes using ion implantation and anneal process in the epitaxy recess of the source/drain region as taught by Hong to have the method further comprising performing a doping implantation process on the source/drain region, wherein the doping implantation process is performed through the contact opening, in order to achieve low contact resistance (Hong, ¶0077).
Regarding claim 10, Chu in view of Hong discloses the method of claim 1. Further, Chu does not specifically disclose the method further comprising etching a dielectric layer that separates the semiconductor substrate from the source/drain region to extend the contact opening to the source/drain region. However, Hong teaches the method further comprising etching a dielectric layer (e.g., dry etching on the substrate to form backside contact includes etching the BDI 224 made of dielectric material) (Hong, Figs. 2, 3A, 3D, ¶0020, ¶0055, ¶0070, ¶0075) that separates the semiconductor substrate (226) from the source/drain region (216b) to extend the contact opening (202/204) to the source/drain region (261b).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chu/Hong by forming the epitaxy recess in the source/drain region for backside contact extending through the substrate and the dielectric layer as taught by Hong to have the method further comprising etching a dielectric layer that separates the semiconductor substrate from the source/drain region to extend the contact opening to the source/drain region, in order to achieve low contact resistance of the source/drain region (Hong, ¶0075-¶0077).
Claims 3-4 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0290866 to Hong in view of Adusumilli et al. (US Patent No. 9,978,750, hereinafter Adusumilli).
Regarding claim 3, Hong discloses the method of claim 2. Further, Hong does not specifically disclose the method, wherein at a time the anneal process is stopped, the amorphous region is partially crystallized.
However, Adusumilli teaches a method of forming low resistance source/drain contacts by performing an amorphization implantation process to generate an amorphous region (36) (Adusumilli, Fig. 4, Col. 7, lines 51-59; Col. 8, lines 33-48) in the source/drain region (18), and an anneal process to recrystallize the amorphous region (36), wherein at a time the anneal process is stopped, the amorphous region (36) is partially crystallized (e.g., a portion of the amorphous region 36 is crystallized) (Adusumilli, Fig. 5, Col. 8, lines 45-48) at a specific thermal budget (Adusumilli, Fig. 5, Col. 8, lines 49-67; Col. 9, lines 1-31), to provide a lower contact resistance of the source/drain region by recrystallizing amorphous layer without impacting gate structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Hong by performing a fast annealing process at a specific thermal budget to recrystallize a portion of the amorphous layer as taught by Adusumilli to have the method, wherein at a time the anneal process is stopped, the amorphous region is partially crystallized, in order to provide a lower contact resistance of the source/drain region by recrystallizing amorphous layer without impacting gate structure (Adusumilli, Col. 1, lines 10-13; Col. 8, lines 43-67; Col. 9, lines 1-3).
Regarding claim 4, Hong discloses the method of claim 2. Further, Hong does not specifically disclose the method, wherein at a time the anneal process is stopped, the amorphous region is fully crystallized.
However, Adusumilli teaches a method of forming low resistance source/drain contacts by performing an amorphization implantation process to generate an amorphous region (36) (Adusumilli, Fig. 4, Col. 7, lines 51-59; Col. 8, lines 33-48) in the source/drain region (18), and an anneal process to recrystallize the amorphous region (36), wherein at a time the anneal process is stopped, the amorphous region (36) is crystallized to have single crystalline structure (Adusumilli, Fig. 5, Col. 8, lines 45-48) at a specific thermal budget (Adusumilli, Fig. 5, Col. 8, lines 49-67; Col. 9, lines 1-31), to provide a lower contact resistance of the source/drain region by recrystallizing amorphous layer without impacting gate structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Hong by performing a fast annealing process at a specific thermal budget to recrystallize amorphous layer as taught by Adusumilli to have the method, wherein at a time the anneal process is stopped, the amorphous region is fully crystallized, in order to provide a lower contact resistance of the source/drain region by recrystallizing amorphous layer without impacting gate structure (Adusumilli, Col. 1, lines 10-13; Col. 8, lines 43-67; Col. 9, lines 1-3).
Regarding claim 7, Hong discloses the method of claim 6. Further, Hong does not specifically disclose the method, wherein a dopant of a same conductivity type as the source/drain region is implanted by the doping implantation process.
However, Adusumilli teaches a method of forming low resistance source/drain contacts by performing an amorphization implantation process to generate an amorphous region (36) (Adusumilli, Fig. 4, Col. 7, lines 51-59; Col. 8, lines 33-48) in the source/drain region (18), wherein the source/drain region (18) (Adusumilli, Fig. 4, Col. 6, lines 18-20; lines 44-51) is an n-type source/drain region including n-type dopant (e.g., phosphorus), and a dopant (e.g., n-type dopant phosphorus) (Adusumilli, Fig. 4, Col. 7, lines 18-20; lines 51-67; Col. 8, lines 1-4) of a same conductivity type as the source/drain region is implanted by the doping implantation process.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Hong by performing an amorphization implantation process by using n-type dopant element as taught by Adusumilli to have the method, wherein a dopant of a same conductivity type as the source/drain region is implanted by the doping implantation process, in order to provide a lower contact resistance of the source/drain region (Adusumilli, Col. 1, lines 10-13; Col. 6, lines 44-51; Col. 8, lines 43-67; Col. 9, lines 1-3).
Regarding claims 8 and 9, Hong discloses the method of claim 1. Further, Hong does not specifically disclose the method, wherein an inert element is introduced into the source/drain region by the amorphization implantation process (as claim in claim 8); wherein a group-IV element is introduced into the source/drain region by the amorphization implantation process (as claim in claim 9).
However, Adusumilli teaches a method of forming low resistance source/drain contacts by performing an amorphization implantation process to generate an amorphous region (36) (Adusumilli, Fig. 4, Col. 7, lines 51-59; Col. 8, lines 33-48) in the source/drain region (18), wherein the source/drain region (18) (Adusumilli, Fig. 4, Col. 6, lines 18-20; lines 44-51) is an n-type source/drain region including n-type dopant (e.g., phosphorus), and an inert element (e.g., Xe) is introduced into the source/drain region by the amorphization implantation process (Adusumilli, Fig. 4, Col. 7, lines 51-54; Col. 8, lines 5-32), or wherein a group-IV element (e.g., Si or Ge) is introduced into the source/drain region by the amorphization implantation process.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Hong by performing an amorphization implantation process by using n-type dopant element as taught by Adusumilli to have the method, wherein a dopant of a same conductivity type as the source/drain region is implanted by the doping implantation process (as claim in claim 8); wherein a group-IV element is introduced into the source/drain region by the amorphization implantation process (as claim in claim 9), in order to provide a lower contact resistance of the source/drain region (Adusumilli, Col. 1, lines 10-13; Col. 6, lines 44-51; Col. 8, lines 43-67; Col. 9, lines 1-3).
Claims 3-4 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0012147 to Chu in view of Hong (US 2024/0290866) as applied to claim 2, and further in view of Adusumilli (US Patent No. 9,978,750).
Regarding claim 3, Chu in view of Hong discloses the method of claim 2. Further, Chu does not specifically disclose the method, wherein at a time the anneal process is stopped, the amorphous region is partially crystallized.
However, Adusumilli teaches a method of forming low resistance source/drain contacts by performing an amorphization implantation process to generate an amorphous region (36) (Adusumilli, Fig. 4, Col. 7, lines 51-59; Col. 8, lines 33-48) in the source/drain region (18), and an anneal process to recrystallize the amorphous region (36), wherein at a time the anneal process is stopped, the amorphous region (36) is partially crystallized (e.g., a portion of the amorphous region 36 is crystallized) (Adusumilli, Fig. 5, Col. 8, lines 45-48) at a specific thermal budget (Adusumilli, Fig. 5, Col. 8, lines 49-67; Col. 9, lines 1-31), to provide a lower contact resistance of the source/drain region by recrystallizing amorphous layer without impacting gate structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chu/Hong by performing a fast annealing process at a specific thermal budget to recrystallize a portion of the amorphous layer as taught by Adusumilli to have the method, wherein at a time the anneal process is stopped, the amorphous region is partially crystallized, in order to provide a lower contact resistance of the source/drain region by recrystallizing amorphous layer without impacting gate structure (Adusumilli, Col. 1, lines 10-13; Col. 8, lines 43-67; Col. 9, lines 1-3).
Regarding claim 4, Chu in view of Hong discloses the method of claim 2. Further, Chu does not specifically disclose the method, wherein at a time the anneal process is stopped, the amorphous region is fully crystallized.
However, Adusumilli teaches a method of forming low resistance source/drain contacts by performing an amorphization implantation process to generate an amorphous region (36) (Adusumilli, Fig. 4, Col. 7, lines 51-59; Col. 8, lines 33-48) in the source/drain region (18), and an anneal process to recrystallize the amorphous region (36), wherein at a time the anneal process is stopped, the amorphous region (36) is crystallized to have single crystalline structure (Adusumilli, Fig. 5, Col. 8, lines 45-48) at a specific thermal budget (Adusumilli, Fig. 5, Col. 8, lines 49-67; Col. 9, lines 1-31), to provide a lower contact resistance of the source/drain region by recrystallizing amorphous layer without impacting gate structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chu/Hong by performing a fast annealing process at a specific thermal budget to recrystallize amorphous layer as taught by Adusumilli to have the method, wherein at a time the anneal process is stopped, the amorphous region is fully crystallized, in order to provide a lower contact resistance of the source/drain region by recrystallizing amorphous layer without impacting gate structure (Adusumilli, Col. 1, lines 10-13; Col. 8, lines 43-67; Col. 9, lines 1-3).
Regarding claim 7, Chu in view of Hong discloses the method of claim 6. Further, Chu does not specifically disclose the method, wherein a dopant of a same conductivity type as the source/drain region is implanted by the doping implantation process.
However, Adusumilli teaches a method of forming low resistance source/drain contacts by performing an amorphization implantation process to generate an amorphous region (36) (Adusumilli, Fig. 4, Col. 7, lines 51-59; Col. 8, lines 33-48) in the source/drain region (18), wherein the source/drain region (18) (Adusumilli, Fig. 4, Col. 6, lines 18-20; lines 44-51) is an n-type source/drain region including n-type dopant (e.g., phosphorus), and a dopant (e.g., n-type dopant phosphorus) (Adusumilli, Fig. 4, Col. 7, lines 18-20; lines 51-67; Col. 8, lines 1-4) of a same conductivity type as the source/drain region is implanted by the doping implantation process.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chu/Hong by performing an amorphization implantation process by using n-type dopant element as taught by Adusumilli to have the method, wherein a dopant of a same conductivity type as the source/drain region is implanted by the doping implantation process, in order to provide a lower contact resistance of the source/drain region (Adusumilli, Col. 1, lines 10-13; Col. 6, lines 44-51; Col. 8, lines 43-67; Col. 9, lines 1-3).
Regarding claims 8 and 9, Chu in view of Hong discloses the method of claim 1. Further, Chu does not specifically disclose the method, wherein an inert element is introduced into the source/drain region by the amorphization implantation process (as claim in claim 8); wherein a group-IV element is introduced into the source/drain region by the amorphization implantation process (as claim in claim 9).
However, Adusumilli teaches a method of forming low resistance source/drain contacts by performing an amorphization implantation process to generate an amorphous region (36) (Adusumilli, Fig. 4, Col. 7, lines 51-59; Col. 8, lines 33-48) in the source/drain region (18), wherein the source/drain region (18) (Adusumilli, Fig. 4, Col. 6, lines 18-20; lines 44-51) is an n-type source/drain region including n-type dopant (e.g., phosphorus), and an inert element (e.g., Xe) is introduced into the source/drain region by the amorphization implantation process (Adusumilli, Fig. 4, Col. 7, lines 51-54; Col. 8, lines 5-32), or wherein a group-IV element (e.g., Si or Ge) is introduced into the source/drain region by the amorphization implantation process.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chu/Hong by performing an amorphization implantation process by using n-type dopant element as taught by Adusumilli to have the method, wherein a dopant of a same conductivity type as the source/drain region is implanted by the doping implantation process (as claim in claim 8); wherein a group-IV element is introduced into the source/drain region by the amorphization implantation process (as claim in claim 9), in order to provide a lower contact resistance of the source/drain region (Adusumilli, Col. 1, lines 10-13; Col. 6, lines 44-51; Col. 8, lines 43-67; Col. 9, lines 1-3).
Claims 11-13 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0012147 to Chu in view of Hong (US 2024/0290866) and Adusumilli (US Patent No. 9,978,750).
With respect to claims 11-13, Chu discloses a method (e.g., forming backside contact structure in a semiconductor device) (Chu, Figs. 2A-2D, 4-10, 14-15, ¶0001, ¶0016-¶0020, ¶0044-¶0074) comprising:
forming a transistor (e.g., FETs 102A/102B) (Chu, Figs. 2A-2B, 4-6, ¶0022-¶0031, ¶0047-¶0050) over a semiconductor substrate (406), the forming the transistor (102A/102B) comprising:
forming a plurality of semiconductor nanostructures (e.g., channel structures 122 of the nanosheet layers) (Chu Figs. 2A-2B, 4-6, ¶0025, ¶0049) over the semiconductor substrate (226); and
performing an epitaxy process (Chu, Figs. 2A-2B, 4-6, ¶0027-¶0028, ¶0050) to form an epitaxy region (e.g., 110A/110B) connected to the plurality of semiconductor nanostructures (122), wherein in the epitaxy process, a first dopant of n-type or p- type is in-situ doped (Chu, Figs. 2A-2B, 4-6, ¶0028) into the epitaxy region (110A/100B);
forming a contact opening (e.g., 1064A/1064B) (Chu, Figs. 10, 14, ¶0054, ¶0064) extending from a back surface of the semiconductor substrate (406) to the epitaxy region (110A/110B); and
forming a contact plug (e.g., metal contact 150) (Chu, Fig. 15, ¶0064-¶0072) to fill the contact opening (e.g., 1064A/1064B).
Further, Chu does not specifically disclose the method comprising: performing an amorphization implantation process through the contact opening to generate an amorphous region in the epitaxy region; performing a doping implantation process to introduce a second dopant of a same conductivity type as the first dopant into the epitaxy region (as claimed in claim 11); wherein an element selected from a group-IV element is introduced into the epitaxy region by the amorphization implantation process (as claimed in claim 12); wherein an inert gas is introduced into the epitaxy region by the amorphization implantation process (as claimed in claim 13).
However, Hong teaches a method of forming a backside contact structure in a semiconductor device (Hong, Figs. 2, 3A-3G, ¶0002, ¶0019-¶0025, ¶0054-¶0090) comprising performing an amorphization implantation process (Hong, Figs. 2, 3E, ¶0076) by using an implantation to generate an amorphous region in the epitaxy recess of the source/drain region, and recrystallization epi by using a laser anneal process, to make a good silicide in the subsequent steps to achieve low contact resistance (Hong, ¶0075-¶0077).
Further, Adusumilli teaches a method of forming low resistance source/drain contacts by performing an amorphization implantation process to generate an amorphous region (36) (Adusumilli, Fig. 4, Col. 7, lines 51-59; Col. 8, lines 33-48) in the source/drain region (18), wherein the source/drain region (18) (Adusumilli, Fig. 4, Col. 6, lines 18-20; lines 44-51) is an n-type source/drain region including n-type dopant (e.g., phosphorus), and a dopant (e.g., n-type dopant phosphorus) (Adusumilli, Fig. 4, Col. 7, lines 18-20; lines 51-67; Col. 8, lines 1-4) of a same conductivity type as the source/drain region is implanted by the doping implantation process, wherein an inert element (e.g., Xe) is introduced into the source/drain region by the amorphization implantation process (Adusumilli, Fig. 4, Col. 7, lines 51-54; Col. 8, lines 5-32) or a group-IV element (e.g., Si or Ge) is introduced into the source/drain region by the amorphization implantation process.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chu by performing amorphization epi and recrystallization epi processes using ion implantation and anneal process in the epitaxy recess of the source/drain region as taught by Hong, wherein the amorphization implantation process is performed by using n-type dopant element or neutral species as taught by Adusumilli to have the method comprising: performing an amorphization implantation process through the contact opening to generate an amorphous region in the epitaxy region; performing a doping implantation process to introduce a second dopant of a same conductivity type as the first dopant into the epitaxy region (as claimed in claim 11); wherein an element selected from a group-IV element is introduced into the epitaxy region by the amorphization implantation process (as claimed in claim 12); wherein an inert gas is introduced into the epitaxy region by the amorphization implantation process (as claimed in claim 13), to make a good silicide in the subsequent steps to achieve low contact resistance; and to provide a lower contact resistance of the source/drain region (Hong, ¶0075-¶0077; Adusumilli, Col. 1, lines 10-13; Col. 6, lines 44-51; Col. 8, lines 43-67; Col. 9, lines 1-3).
Regarding claim 16, Chu in view of Hong and Adusumilli discloses the method of claim 11. Further, Chu discloses the method further comprising forming a silicide region (e.g., 148B-2/148B-1) (Chu, Figs. 14, 15, ¶0065-¶0072) on the epitaxy region (110A/110B).
Regarding claim 17, Chu in view of Hong and Adusumilli discloses the method of claim 11. Further, Chu does not specifically disclose the method further comprising an anneal process to partially crystallize the amorphous region.
However, Adusumilli teaches a method of forming low resistance source/drain contacts by performing an amorphization implantation process to generate an amorphous region (36) (Adusumilli, Fig. 4, Col. 7, lines 51-59; Col. 8, lines 33-48) in the source/drain region (18), and an anneal process to recrystallize the amorphous region (36), wherein the amorphous region (36) is partially crystallized (e.g., a portion of the amorphous region 36 is crystallized) (Adusumilli, Fig. 5, Col. 8, lines 45-48) at a specific thermal budget (Adusumilli, Fig. 5, Col. 8, lines 49-67; Col. 9, lines 1-31), to provide a lower contact resistance of the source/drain region by recrystallizing amorphous layer without impacting gate structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chu/Hong/Adusumilli by performing a fast annealing process at a specific thermal budget to recrystallize a portion of the amorphous layer as taught by Adusumilli to have the method further comprising an anneal process to partially crystallize the amorphous region, in order to provide a lower contact resistance of the source/drain region by recrystallizing amorphous layer without impacting gate structure (Adusumilli, Col. 1, lines 10-13; Col. 8, lines 43-67; Col. 9, lines 1-31).
With respect to claim 18, Chu discloses a method (e.g., forming backside contact structure in a semiconductor device) (Chu, Figs. 2A-2D, 4-10, 14-15, ¶0001, ¶0016-¶0020, ¶0044-¶0074) comprising:
forming a transistor (e.g., FETs 102A/102B) (Chu, Figs. 2A-2B, 4-6, ¶0022-¶0031, ¶0047-¶0050) over a semiconductor substrate (406), the forming the transistor (102A/102B) comprising:
forming a plurality of semiconductor nanostructures (e.g., channel structures 122 of the nanosheet layers) (Chu Figs. 2A-2B, 4-6, ¶0025, ¶0049) over the semiconductor substrate (226); and
performing an epitaxy process (Chu, Figs. 2A-2B, 4-6, ¶0027-¶0028, ¶0050) to form an epitaxy region (e.g., 110A/110B) connected to the plurality of semiconductor nanostructures (122);
forming a contact opening (e.g., 1064A/1064B) (Chu, Figs. 10, 14, ¶0054, ¶0064) from a backside of the semiconductor substrate (406) to reveal the epitaxy region (110A/110B); and
forming a silicide region (e.g., 148B-2/148B-1) (Chu, Figs. 14, 15, ¶0065-¶0072) based on a part of the epitaxy region (110A/110B).
Further, Chu does not specifically disclose the method comprising: performing an amorphization implantation process on the epitaxy region to form an amorphous region; performing a first anneal process to partially anneal the amorphous region; and forming a silicide region based on a part of the epitaxy region that is implanted by the amorphization implantation process.
However, Hong teaches a method of forming a backside contact structure in a semiconductor device (Hong, Figs. 2, 3A-3G, ¶0002, ¶0019-¶0025, ¶0054-¶0090) comprising performing an amorphization implantation process (Hong, Figs. 2, 3E, ¶0076) by using an implantation to generate an amorphous region in the epitaxy recess of the source/drain region, and recrystallization epi by using a laser anneal process, to make a good silicide in the subsequent steps to achieve low contact resistance (Hong, ¶0075-¶0077).
Further, Adusumilli teaches a method of forming low resistance source/drain contacts by performing an amorphization implantation process to generate an amorphous region (36) (Adusumilli, Fig. 4, Col. 7, lines 51-59; Col. 8, lines 33-48) in the source/drain region (18), wherein the amorphous region (36) is partially crystallized (e.g., a portion of the amorphous region 36 is crystallized) (Adusumilli, Fig. 5, Col. 8, lines 45-48) at a specific thermal budget (Adusumilli, Fig. 5, Col. 8, lines 49-67; Col. 9, lines 1-31), to provide a lower contact resistance of the source/drain region by recrystallizing amorphous layer without impacting gate structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chu by performing amorphization epi and recrystallization epi processes using ion implantation and anneal process in the epitaxy recess of the source/drain region as taught by Hong, wherein a fast annealing process is performed at a specific thermal budget to recrystallize a portion of the amorphous layer as taught by Adusumilli to have the method comprising: performing an amorphization implantation process on the epitaxy region to form an amorphous region; performing a first anneal process to partially anneal the amorphous region; and forming a silicide region based on a part of the epitaxy region that is implanted by the amorphization implantation process, to make a good silicide in the subsequent steps to achieve low contact resistance; and to provide a lower contact resistance of the source/drain region by recrystallizing amorphous layer without impacting gate structure (Hong, ¶0075-¶0077; Adusumilli, Col. 1, lines 10-13; Col. 6, lines 44-51; Col. 8, lines 43-67; Col. 9, lines 1-31).
Regarding claim 19, Chu in view of Hong and Adusumilli discloses the method of claim 18. Further, Chu does not specifically disclose the method further comprising performing a second anneal process during the forming the silicide region, wherein the first anneal process and the second anneal process are separate anneal processes.
However, Hong teaches the method further comprising performing a second anneal process (e.g., a laser annealing step to form a silicide region 272 in Fig. 3G) (Hong, Figs. 2, 3F-3G, ¶0077-¶0079) during the forming the silicide region, wherein the first anneal process and the second anneal process are separate anneal processes (e.g., a laser annealing step to form the silicide region 272 in Fig. 3G is different from a laser anneal to form recrystallization epi in Fig. 3E).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chu/Hong/Adusumilli by performing amorphization epi and recrystallization epi processes using ion implantation and anneal process and forming the silicide region by performing a second anneal process as taught by Hong to have the method further comprising performing a second anneal process during the forming the silicide region, wherein the first anneal process and the second anneal process are separate anneal processes, in order to provide a good silicide to achieve low contact resistance of the source/drain region (Hong, ¶0075-¶0077).
Regarding claim 20, Chu in view of Hong and Adusumilli discloses the method of claim 18. Further, Chu discloses the method further comprising forming a contact plug (e.g., metal contact 150) (Chu, Fig. 15, ¶0064-¶0072) in the contact opening (e.g., 1064A/1064B).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0012147 to Chu in view of Hong (US 2024/0290866) and Adusumilli (US Patent No. 9,978,750) as applied to claim 11, and further in view of JangJian et al. (US 2015/0255602, hereinafter JangJian).
Regarding claims 14 and 15, Chu in view of Hong and Adusumilli discloses the method of claim 11. Further, Chu does not specifically disclose the method, wherein the amorphization implantation process is performed before the doping implantation process (as claimed in claim 14); wherein the amorphization implantation process is performed after the doping implantation process (as claimed in claim 15).
However, Hong teaches a method of forming a backside contact structure in a semiconductor device (Hong, Figs. 2, 3A-3G, ¶0002, ¶0019-¶0025, ¶0054-¶0090) comprising performing an amorphization implantation process (Hong, Figs. 2, 3E, ¶0076-¶0077) to generate an amorphous region in the epitaxy recess of the source/drain region, and a doping process to achieve low contact resistance (Hong, ¶0075-¶0077).
Further, JangJian teaches a method of forming an integrated circuit (JangJian, Figs. 2-11, ¶0009-¶0031) comprising a transistor with improved performance, wherein the amorphization implantation process (e.g., a first pre-amorphization implantation (PAI)) to form a first amorphous region (320) (JangJian, Fig. 3, ¶0016) within a source/drain region (310) is performed before the doping implantation process (e.g., a second implantation process (PAI)) (JangJian, Fig. 8, ¶0024) to implant various implant species including As, Si, or Ge; or wherein the amorphization implantation process (e.g., a second pre-amorphization implantation (PAI)) (JangJian, Fig. 8, ¶0024) to form a second amorphous region (520) within a source/drain region is performed after the doping implantation process (e.g., a first implantation process (PAI)) (JangJian, Fig. 3, ¶0016), to implant various implant species including As, Si, or Ge, to increase charge mobility through a channel of the transistor (JangJian, ¶0015).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chu/Hong/Adusumilli by performing amorphization epi process and a doping process as taught by Hong, wherein a first/second amorphization process performed before/after a doping process as taught by JangJian to have the method, wherein the amorphization implantation process is performed before the doping implantation process (as claimed in claim 14); wherein the amorphization implantation process is performed after the doping implantation process (as claimed in claim 15), in order to achieve low contact resistance of the source/drain region; and to increase charge mobility through a channel of the transistor (Hong, ¶0075-¶0077; JangJian, ¶0015).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
Prosecution Insights