DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 11-14 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites
A semiconductor wafer handling apparatus that moves a semiconductor wafer including a device under test (DUT) and presses a terminal of the DUT against a contactor of a probe card, the semiconductor wafer handling apparatus comprising:
an optical probe that inputs and outputs an optical signal to and from an optical connection part of the DUT, wherein
the terminal is disposed on a first surface of the semiconductor wafer, and
the optical connection part is disposed on a second surface of the semiconductor wafer.
The claim language recites a semiconductor wafer handling apparatus that performs the functions of moving a semiconductor wafer including a DUT and pressing a terminal of the DUT against a contactor of a probe card. However, the only affirmatively recited structure of the semiconductor wafer handling apparatus is an optical probe that inputs and outputs an optical signal to and from an optical connection part of the DUT. Consequently, the claim does not appear to recite the requisite structure for performing the claimed moving and pressing functionality. As such, the boundaries of the functional language are unclear because the claim does not provide a discernable boundary on what performs the functions. The recited function does not follow from the structure recited in the claim, so it is unclear whether the function requires some other structure or is simply a result of operating the semiconductor wafer handling apparatus. Thus one of ordinary skill would not be able to draw a clear boundary between what is and is not covered by the claim. See MPEP 2173.05(g). Clarification is required. For purposes of the present examination, the language “that moves a semiconductor wafer including a device under test (DUT) and presses a terminal of the DUT against a contactor of a probe card” is in interpreted as merely setting forth the purpose or intended use of the invention, rather than any distinct definition of any of the claimed invention’s limitations. Claims 2-8, 11-14 and 16 are rejected under 35 U.S.C. 112(b) by virtue of their dependence from claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by applicant-cited US 2021/0190860 to Sameshima (Sameshima).
Regarding claim 1, Sameshima discloses a semiconductor wafer handling apparatus that moves a semiconductor wafer including a device under test (DUT) and presses a terminal of the DUT against a contactor of a probe card, the semiconductor wafer handling apparatus comprising:
an optical probe that inputs and outputs an optical signal to and from an optical connection part of the DUT (Sameshima, e.g., Fig. 1 and paragraphs 18-43; Fig. 1 discloses a double-sided probe systems 10 configured to test one or more devices under test (DUTs) 40, which may be formed on, supported by, and/or included in a substrate 30; see, e.g., paragraph 21, substrate 30 may be a wafer; also see paragraph 24, chuck 20 also may be described as being configured to support substrate 30 such that probe assembly 100 is operable to test each of first substrate side 32 and second substrate side 34 concurrently and/or without repositioning substrate 30 upon chuck 20; see, e.g., paragraph 24, probe assembly 100 is operable to test each of first substrate side 32 and second substrate side 34 concurrently and/or without repositioning substrate 30 upon chuck 20; for example, probe assembly 100 may be configured to test one of first substrate side 32 and second substrate side 34 via an electrical connection, such as by providing an electrical signal, and concurrently, probe assembly 100 may be configured to test the other of first substrate side 32 and second substrate side 34 via an optical measurement, such as by receiving an optical signal, such as may correspond to, or result from, the electrical signal supplied to the opposite side of substrate 30; see, e.g., paragraph 25, probe assembly 100 may be configured to transmit a test signal 52 to first substrate side 32 and/or to second substrate side 34 and/or to receive a resultant signal 54 from first substrate side 32 and/or from second substrate side 34; test signal 52 may include and/or be any of a variety of signals, examples of which include an electric test signal, a direct current test signal, an alternating current test signal, an analog test signal, a digital test signal, and/or an optical test signal; also see paragraph 36, probe assembly 100 and/or each probe 130 thereof may be configured to interface with one or more testing locations 42 of substrate 30 to test the substrate; each DUT 40 includes at least one corresponding testing location 42, and each testing location 42 may include and/or be a contact pad, a solder bump, an optical coupler, etc.; also see paragraph 37, at least one probe 130 may be configured for non-contact testing of DUT 40; for example, at least one probe 130 may be an optical probe and/or a probe antenna, such as a probe that is configured to be optically and/or electromagnetically coupled to testing location 42 for non-contact testing of DUT 40).
Regarding the language wherein
the terminal is disposed on a first surface of the semiconductor wafer, and
the optical connection part is disposed on a second surface of the semiconductor wafer,
the examiner notes that the DUT is not affirmatively recited as an element of the claimed invention, but rather as a structure with which the claimed invention is to be used. Accordingly, structural features of the DUT do not carry patentable weight. Nonetheless, for purposes of compact prosecution, the examiner notes that Sameshima does discloses a DUT having the recited features (Sameshima, e.g., paragraph 24).
Regarding claim 2, Sameshima discloses a first moving device that moves the optical probe relative to the semiconductor wafer (Sameshima, e.g., Fig. 1 and paragraphs 61-64, positioner stage 120).
Regarding claim 13, Sameshima discloses wherein the optical probe comprises an optical transmission path that transmits the optical signal (see Sameshima as applied to claim 1, e.g., paragraph 25, test signal 52 may include and/or be any of a variety of signals, examples of which include an electric test signal, a direct current test signal, an alternating current test signal, an analog test signal, a digital test signal, and/or an optical test signal; the examiner notes that in the case of an optical signal, an optical transmission path is implied).
Claim 14 recites wherein the optical connection part includes a grating coupler. The examiner notes that the DUT (and therefore a grating coupler) is not affirmatively recited as an element of the claimed semiconductor wafer handling apparatus. Accordingly, features of the DUT, such as a grating coupler, do not carry patentable weight.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Sameshima.
Regarding claim 15, Sameshima discloses a semiconductor wafer testing system that tests a device under test (DUT) in a semiconductor wafer, comprising:
a probe arrangement that inputs and outputs an electrical signal to and from a terminal of the DUT (Sameshima, e.g., Fig. 1 and paragraphs 18-43; see, e.g., paragraph 37, each probe 130 may have any appropriate form and/or structure for testing DUT 40; as an example, probe 130 may be a vertical probe, such as may be configured to contact testing location 42 in the form of a solder bump of a corresponding DUT 40; as another example, and as schematically illustrated in FIG. 1, probe 130 may be a cantilever probe that is configured to contact testing location 42 in the form of a contact pad of a corresponding DUT 40);
an optical probe that inputs and outputs an optical signal to and from an optical connection part of the DUT (Sameshima, e.g., Fig. 1 and paragraphs 18-43; Fig. 1 discloses a double-sided probe systems 10 configured to test one or more devices under test (DUTs) 40, which may be formed on, supported by, and/or included in a substrate 30; see, e.g., paragraph 21, substrate 30 may be a wafer; also see paragraph 24, chuck 20 also may be described as being configured to support substrate 30 such that probe assembly 100 is operable to test each of first substrate side 32 and second substrate side 34 concurrently and/or without repositioning substrate 30 upon chuck 20; see, e.g., paragraph 24, probe assembly 100 is operable to test each of first substrate side 32 and second substrate side 34 concurrently and/or without repositioning substrate 30 upon chuck 20; for example, probe assembly 100 may be configured to test one of first substrate side 32 and second substrate side 34 via an electrical connection, such as by providing an electrical signal, and concurrently, probe assembly 100 may be configured to test the other of first substrate side 32 and second substrate side 34 via an optical measurement, such as by receiving an optical signal, such as may correspond to, or result from, the electrical signal supplied to the opposite side of substrate 30; see, e.g., paragraph 25, probe assembly 100 may be configured to transmit a test signal 52 to first substrate side 32 and/or to second substrate side 34 and/or to receive a resultant signal 54 from first substrate side 32 and/or from second substrate side 34; test signal 52 may include and/or be any of a variety of signals, examples of which include an electric test signal, a direct current test signal, an alternating current test signal, an analog test signal, a digital test signal, and/or an optical test signal; also see paragraph 36, probe assembly 100 and/or each probe 130 thereof may be configured to interface with one or more testing locations 42 of substrate 30 to test the substrate; each DUT 40 includes at least one corresponding testing location 42, and each testing location 42 may include and/or be a contact pad, a solder bump, an optical coupler, etc.; also see paragraph 37, at least one probe 130 may be configured for non-contact testing of DUT 40; for example, at least one probe 130 may be an optical probe and/or a probe antenna, such as a probe that is configured to be optically and/or electromagnetically coupled to testing location 42 for non-contact testing of DUT 40); and
a testing device connected to the probe card and the optical probe to transmit the electrical signal and the optical signal, respectively (Sameshima, e.g., Fig. 1 and paragraphs 18-43; see, e.g., paragraph 25, probe assembly 100 may be configured to transmit a test signal 52 to first substrate side 32 and/or to second substrate side 34 and/or to receive a resultant signal 54 from first substrate side 32 and/or from second substrate side 34; test signal 52 may include and/or be any of a variety of signals, examples of which include an electric test signal, a direct current test signal, an alternating current test signal, an analog test signal, a digital test signal, and/or an optical test signal; in some examples, and as schematically illustrated in FIG. 1, double-sided probe systems 10 additionally include a signal generation and analysis assembly 50 that is configured to provide test signal 52 to probe assembly 100 and/or to receive resultant signal 54 from probe assembly 100), wherein
the terminal is disposed on a first surface of the semiconductor wafer (Sameshima, e.g., paragraph 24, probe assembly 100 is operable to test each of first substrate side 32 and second substrate side 34 concurrently and/or without repositioning substrate 30 upon chuck 20; for example, probe assembly 100 may be configured to test one of first substrate side 32 and second substrate side 34 via an electrical connection, such as by providing an electrical signal, and concurrently, probe assembly 100 may be configured to test the other of first substrate side 32 and second substrate side 34 via an optical measurement, such as by receiving an optical signal, such as may correspond to, or result from, the electrical signal supplied to the opposite side of substrate 30; note as shown Fig 1 that probe 130 may be a cantilever probe, which implies the terminal is disposed on first substrate side 32), and
the optical connection part is disposed on a second surface of the semiconductor wafer (Sameshima, e.g., paragraph 24, probe assembly 100 is operable to test each of first substrate side 32 and second substrate side 34 concurrently and/or without repositioning substrate 30 upon chuck 20; for example, probe assembly 100 may be configured to test one of first substrate side 32 and second substrate side 34 via an electrical connection, such as by providing an electrical signal, and concurrently, probe assembly 100 may be configured to test the other of first substrate side 32 and second substrate side 34 via an optical measurement, such as by receiving an optical signal, such as may correspond to, or result from, the electrical signal supplied to the opposite side of substrate 30).
Sameshima is not relied upon as explicitly disclosing that the probe arrangement for inputting and outputting an electrical signal to and from the terminal of the DUT (e.g., probe 130 including cantilever probes as shown in Fig. 1) is or includes a probe card. The examiner takes Official notice of the fact that the use of a probe card in combination with cantilever probes of the type disclosed in Fig. 1 was well-known and conventional before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. See, e.g., Probe Card Tutorial, available at https://www.tek.com/en/documents/whitepaper/probe-card-tutorial on 5/29/2023. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sameshima such that Sameshima’s probe arrangement (e.g., probe 130 including cantilever probes as shown in Fig. 1) is or includes a probe card in view of the well-known and conventional use of probe cards for holding/retaining probes in a desired orientation during testing, and for providing an electrical interface between the probes and testing equipment.
Regarding claim 16, Sameshima discloses a semiconductor wafer testing system that tests the DUT, comprising:
the semiconductor wafer handling apparatus according to claim 1 (see Sameshima as applied to claim 1 above);
the probe arrangement that inputs and outputs an electrical signal to and from the terminal of the DUT (Sameshima, e.g., Fig. 1 and paragraphs 18-43; see, e.g., paragraph 37, each probe 130 may have any appropriate form and/or structure for testing DUT 40; as an example, probe 130 may be a vertical probe, such as may be configured to contact testing location 42 in the form of a solder bump of a corresponding DUT 40; as another example, and as schematically illustrated in FIG. 1, probe 130 may be a cantilever probe that is configured to contact testing location 42 in the form of a contact pad of a corresponding DUT 40); and
a testing device connected to the probe arrangement and the optical probe to transmit the electrical signal and the optical signal, respectively (Sameshima, e.g., Fig. 1 and paragraphs 18-43; see, e.g., paragraph 25, probe assembly 100 may be configured to transmit a test signal 52 to first substrate side 32 and/or to second substrate side 34 and/or to receive a resultant signal 54 from first substrate side 32 and/or from second substrate side 34; test signal 52 may include and/or be any of a variety of signals, examples of which include an electric test signal, a direct current test signal, an alternating current test signal, an analog test signal, a digital test signal, and/or an optical test signal; in some examples, and as schematically illustrated in FIG. 1, double-sided probe systems 10 additionally include a signal generation and analysis assembly 50 that is configured to provide test signal 52 to probe assembly 100 and/or to receive resultant signal 54 from probe assembly 100).
Sameshima is not relied upon as explicitly disclosing that the probe arrangement for inputting and outputting an electrical signal to and from the terminal of the DUT (e.g., probe 130 including cantilever probes as shown in Fig. 1) is or includes a probe card. The examiner takes Official notice of the fact that the use of a probe card in combination with cantilever probes of the type disclosed in Fig. 1 was well-known and conventional before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. See, e.g., Probe Card Tutorial, available at https://www.tek.com/en/documents/whitepaper/probe-card-tutorial on 5/29/2023. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sameshima such that Sameshima’s probe arrangement (e.g., probe 130 including cantilever probes as shown in Fig. 1) is or includes a probe card in view of the well-known and conventional use of probe cards for holding/retaining probes in a desired orientation during testing, and for providing an electrical interface between the probes and testing equipment.
Claims 3 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sameshima in view of US 2020/0378888 to Negishi et al. (Negishi).
Regarding claim 3, Sameshima discloses:
a holding member that holds the semiconductor wafer (Sameshima, e.g., Fig. 1, chuck 20); and
wherein
the first moving device moves the optical probe relative to the semiconductor wafer held by the holding member (see Sameshima as applied to claim 2, Fig. 1, positioner stage 120 moves probe head 140 relative to chuck 20).
Sameshima is not relied upon as explicitly disclosing a second moving device that moves the holding member relative to the probe card. In related art, Negishi discloses an optical probe system configured to permit and/or facilitate operative translation and/or rotation of device substrate chuck relative to one or more other components of the optical probe system (Negishi, e.g. paragraph 33). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sameshima to include a second moving device that moves the holding member relative to the probe card. In this way, in the manner disclosed by Negishi, Sameshima’s holding member (e.g., chuck 20) can be moved/adjusted as need to position substrate 30/DUTs 40 as necessary for testing/inspection.
Regarding claim 11, Sameshima in view of Negishi discloses wherein the holding member holds either an outer peripheral part of the first surface of the semiconductor wafer or an outer peripheral part of the second surface of the semiconductor wafer such that the first and second surfaces are exposed (Sameshima, e.g., Fig. 1, noting that chuck 20 holds an outer peripheral part of the second substrate surface 34 of the substrate 30 such that first and second substrate surfaces 32, 34 are exposed).
Regarding claim 12, Sameshima in view of Negishi discloses wherein the holding member comprises an annular holding part that holds either an outer peripheral part of the first surface of the semiconductor wafer or an outer peripheral part of the second surface of the semiconductor wafer (Sameshima, e.g., Fig. 1, noting that chuck 20 comprises an annular holding part that holds an outer peripheral part of the second substrate surface 34 of the substrate 30, which may be a semiconductor wafer).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Sameshima in view of US 2021/0096175 to Frankel (Frankel) and US 2020/0378888 to Negishi et al. (Negishi).
Regarding claim 9, Sameshima discloses a semiconductor wafer handling apparatus that moves a semiconductor wafer including device under tests (DUTs) and presses terminals of the DUTs against contactors of a probe the semiconductor wafer handling apparatus comprising:
N optical probes each of which inputs and outputs an optical signal to and from each of a plurality of optical connection parts of the DUTs, respectively where the N is a natural number between 1 and 8, inclusive (Sameshima, e.g., Fig. 1 and paragraphs 18-43; Fig. 1 discloses a double-sided probe systems 10 configured to test one or more devices under test (DUTs) 40, which may be formed on, supported by, and/or included in a substrate 30; see, e.g., paragraph 21, substrate 30 may be a wafer; also see paragraph 24, chuck 20 also may be described as being configured to support substrate 30 such that probe assembly 100 is operable to test each of first substrate side 32 and second substrate side 34 concurrently and/or without repositioning substrate 30 upon chuck 20; see, e.g., paragraph 24, probe assembly 100 is operable to test each of first substrate side 32 and second substrate side 34 concurrently and/or without repositioning substrate 30 upon chuck 20; for example, probe assembly 100 may be configured to test one of first substrate side 32 and second substrate side 34 via an electrical connection, such as by providing an electrical signal, and concurrently, probe assembly 100 may be configured to test the other of first substrate side 32 and second substrate side 34 via an optical measurement, such as by receiving an optical signal, such as may correspond to, or result from, the electrical signal supplied to the opposite side of substrate 30; see, e.g., paragraph 25, probe assembly 100 may be configured to transmit a test signal 52 to first substrate side 32 and/or to second substrate side 34 and/or to receive a resultant signal 54 from first substrate side 32 and/or from second substrate side 34; test signal 52 may include and/or be any of a variety of signals, examples of which include an electric test signal, a direct current test signal, an alternating current test signal, an analog test signal, a digital test signal, and/or an optical test signal; also see paragraph 36, probe assembly 100 and/or each probe 130 thereof may be configured to interface with one or more testing locations 42 of substrate 30 to test the substrate; each DUT 40 includes at least one corresponding testing location 42, and each testing location 42 may include and/or be a contact pad, a solder bump, an optical coupler, etc.; also see paragraph 37, at least one probe 130 may be configured for non-contact testing of DUT 40; for example, at least one probe 130 may be an optical probe and/or a probe antenna, such as a probe that is configured to be optically and/or electromagnetically coupled to testing location 42 for non-contact testing of DUT 40; the examiner notes that Fig. 1 of Sameshima discloses two DUTs 40, each with two testing locations 42 on the second substrate side 34 opposite the first substrate side 32 which is tested electrically with cantilever probes; this arrangement implies four optical probes, e.g., two optical probes for interfacing with two testing locations 42 on the second substrate side 34 of each DUT 40), wherein
the terminals are disposed on a first surface of the semiconductor wafer (see Sameshima as discussed above, e.g., Fig. 1, two testing locations 42 on the first substrate side 32 of each DUT 40),
the optical connection parts are disposed on a second surface of the semiconductor wafer (see Sameshima as discussed above, e.g., Fig. 1, two testing locations 42 on the second substrate side 34 of each DUT 40),
the semiconductor wafer handling apparatus further comprises:
a holding member that holds the semiconductor wafer (Sameshima, e.g., Fig. 1, chuck 20);
a contact member that contacts the second surface of the semiconductor wafer, the contact member comprises a contact surface that contacts the second surface of the semiconductor wafer,
the contact surface has a size such that the contact surface contacts N DUTs of the DUTs (Sameshima, e.g., paragraph 41, thermal control system 150 is operable to control the substrate temperature via conductive heat transfer, convective heat transfer, and/or radiative heat transfer between one or more components of thermally controlled probe head 140 and substrate 30; the examiner notes that conductive heat transfer implicitly requires contact between a surface of the probe head 140 and DUTs disposed on the substrate 30; also see, e.g., Fig. 8, showing surface of probe head 140 containing probes 130/144),
the N optical probes are disposed to correspond to the N DUTs (see Sameshima as discussed above in connection with the N optical probes), and
Sameshima is not relied upon as explicitly disclosing that the probe arrangement (e.g., probe 130 including cantilever probes as shown in Fig. 1) is or includes a probe card. The examiner takes Official notice of the fact that the use of a probe card in combination with cantilever probes of the type disclosed in Fig. 1 was well-known and conventional before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. See, e.g., Probe Card Tutorial, available at https://www.tek.com/en/documents/whitepaper/probe-card-tutorial on 5/29/2023. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sameshima such that Sameshima’s probe arrangement (e.g., probe 130 including cantilever probes as shown in Fig. 1) is or includes a probe card in view of the well-known and conventional use of probe cards for holding/retaining probes in a desired orientation during testing, and for providing an electrical interface between the probes and testing equipment.
Sameshima is not relied upon as explicitly disclosing N first moving devices each of which moves a corresponding optical probe of the N optical probes relative to the semiconductor wafer held by the holding member and the N first moving devices that each move a corresponding one of the N optical probes. In related art, Frankel discloses an electrically actuated positioning assembly configured to selectively adjust the relative orientation between an optical probe and a DUT (Frankel, e.g., paragraph 25). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sameshima to include N first moving devices each of which moves a corresponding optical probe of the N optical probes relative to the semiconductor wafer held by the holding member such that the N first moving devices that each move a corresponding one of the N optical probes. In this way, in the manner disclosed by Frankel, the absolute position of each of Sameshima’s optical probes relative to the DUT can be suitably adjusted.
Sameshima is not relied upon as explicitly disclosing a second moving device that moves the holding member relative to the probe card. In related art, Negishi discloses an optical probe system configured to permit and/or facilitate operative translation and/or rotation of device substrate chuck relative to one or more other components of the optical probe system (Negishi, e.g. paragraph 33). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sameshima to include a second moving device that moves the holding member relative to the probe card. In this way, in the manner disclosed by Negishi, Sameshima’s holding member (e.g., chuck 20) can be moved/adjusted as need to position substrate 30/DUTs 40 as necessary for testing/inspection.
Regarding claim 10, Sameshima in view of Frankel and Negishi as applied to claim 9 discloses a third moving device that moves the contact member and the N first moving devices relative to the semiconductor wafer held by the holding member (see Sameshima in view of Frankel and Negishi as applied to claim 9, Sameshima, e.g., Fig. 1 and paragraphs 61-64, positioner stage 120; note in modified Sameshima that the N first moving devices will be elements of the probe head 140 moved by positioner stage 120, along with contact surface of the probe head 140 that provides conductive heat transfer to DUTs disposed on the substrate 30).
Allowable Subject Matter
Claims 4-8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 4, the prior art of record as considered and understood by the examiner does not teach or fairly suggest:
a third moving device that moves the contact member and the first moving device relative to the semiconductor wafer held by the holding member,
taken in combination with the other limitations of claim 4. Claims 5-8 would be allowable by virtue of their dependence from claim 4.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 7,145,353 to Hope et al. relates to a probe head that contacts both sides of the semiconducting device under test.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL R MILLER whose telephone number is (571)270-1964. The examiner can normally be reached 9AM-5PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak, can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL R MILLER/Primary Examiner, Art Unit 2858
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