Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the CON application No. 18/817,110 filed on August 27, 2024.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The suggested title of the invention recited as “Semiconductor Chip Package Comprising Recessed Lead Frame with Semiconductor Chip and Manufacturing Method Thereof”.
Claim Objections
6. Claim 13 is objected to because of the following informalities: the following quoted claim should be recited as follows:
13. (Currently Amended) The semiconductor chip package of claim 9, wherein a bottom surface of the semiconductor chip facing the adhesive is in contact with the first surface of the lead frame.
Appropriate correction is needed.
Double Patenting
7. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
8. Claims 1, 4-8, 10-11, 14, 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,113,008 B1. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the instant limitations are recited in or obvious from claims 1-19 of U.S. Patent No. 12,113,008 B1.
Regarding independent claim 1, Lin recites a semiconductor chip package, comprising:
a lead frame having a first surface and a second surface opposite to each other (claim 1, lines 2-3);
a groove recessed from the first surface of the lead frame into the lead frame and completely filled with an adhesive (claim 1, lines 4-5); and
a semiconductor chip disposed on the adhesive in the groove and covering the adhesive, the semiconductor chip being affixed to the lead frame through the adhesive in the groove (claim 1, lines 6-9).
Regarding claim 4, Lin recites wherein, the lead frame further comprises:
a chip pad on which the groove is provided, and a drain lead contact separated from the chip pad (claim 1, lines 10-13); and
the semiconductor chip comprises a drain provided on a bottom surface of the semiconductor chip, the drain being coupled to the drain lead contact via the chip pad, the adhesive and a wire (claim 4, lines 5-10).
Regarding claim 5, Lin recites wherein, further comprising:
a carrier provided on the second surface of the lead frame for carrying the lead frame and the semiconductor chip (claim 5, lines 1-4).
Regarding claim 6, Lin recites wherein, the carrier comprises:
a first portion overlapping with the semiconductor chip (claim 7, lines 2-3); and
a second portion not overlapping with the semiconductor chip (claim 7, lines 3-4), the first portion having a thermal conductivity coefficient greater than that of the second portion (claim 6, lines 4-6).
Regarding claim 7, Lin recites wherein, the second portion of the carrier comprises three external terminals of the semiconductor chip package (claim 8, lines 1-3).
Regarding claim 8, Lin recites wherein, the first portion of the carrier comprises a ceramic portion, and the second portion comprises a metal portion (claim 9, lines 1-3).
Regarding claim 10, Lin recites wherein, the carrier comprises:
a first portion overlapping with the semiconductor chip (claim 12, lines 2-3); and
a second portion not overlapping with the semiconductor chip (claim 12, lines 3-4), the first portion having a thermal conductivity coefficient greater than that of the second portion (claim 11, lines 4-6).
Regarding claim 11, Lin recites wherein, the second portion of the carrier comprises three external terminals of the semiconductor chip package (claim 13, lines 1-3).
Regarding independent claim 14, Lin recites a method for manufacturing a semiconductor chip package, comprising:
obtaining a lead frame, the lead frame having a first surface and a second surface opposite to each other, with a groove recessed from the first surface of the lead frame into the lead frame (claim 14, lines 3-6);
completely filling the groove with an adhesive (claim 14, line 7); and
disposing a semiconductor chip on the adhesive and covering the adhesive, the semiconductor chip being affixed to the lead frame through the adhesive in the groove (claim 14, lines 8-10).
Regarding claim 17, Lin recites wherein, further comprising:
affixing a carrier on the second surface of the lead frame using a clamping device, the clamping device disposed on the first surface of the lead frame (claim 16, lines 3-5).
Regarding claim 18, Lin recites wherein, the carrier comprises:
a first portion (claim 17, lines 1-4) overlapping with the semiconductor chip; and
a second portion, the first portion having a thermal conductivity coefficient greater than that of the second portion (claim 17, lines 3-6).
Regarding claim 19, Lin recites wherein, further comprising:
removing a portion of the second portion of the carrier such that the first portion and the second portion are not in contact with each other (claim 18, lines 1-4).
Regarding claim 20, Lin recites wherein, further comprising:
forming the second portion into three external terminals of the semiconductor chip package, the three external terminals being separated from each other (claim 19, lines 1-4).
Claim Rejections - 35 USC § 102
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
11. Claims 1-3, 5-6, 9-10, 12-16, 18-19 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee et al. (US 2013/0277815 A1).
Regarding independent claim 1, Lee et al. teaches a semiconductor chip package, comprising (Fig. 2I):
a lead frame (10, see Fig. 2C, para [0024]) having a first surface (upper surface) and a second surface (lower surface) opposite to each other;
a groove (see the annotated figure below) recessed from the first surface (upper surface) of the lead frame (10) into the lead frame (10) and completely filled with an adhesive (33, see Fig. 2D, para [0026]); and
a semiconductor chip (14, see Fig. 2D, para [0026]) disposed on the adhesive (33) in the groove and covering the adhesive (33), the semiconductor chip (14) being affixed to the lead frame (10) through the adhesive (33) in the groove.
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Regarding claim 2, Lee et al. teaches wherein (Fig. 2I), a width (d1) of the groove is less than a width (d2) of the semiconductor chip (14).
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Regarding claim 3, Lee et al. teaches wherein (Fig. 2D), a bottom surface of the semiconductor chip (14) facing the adhesive (33) is in contact with the first surface (upper surface) of the lead frame (10).
Regarding claim 5, Lee et al. teaches wherein (Fig. 2D), further comprising:
a carrier (24 called insulating material, para [0023]) provided on the second surface (lower surface) of the lead frame (10) for carrying the lead frame and the semiconductor chip (14).
Regarding claim 6, Lin teaches wherein (Fig. 2I), the carrier (24) comprises:
a first portion (middle) overlapping with the semiconductor chip (14); and
a second portion (sides) not overlapping with the semiconductor chip (14), the first portion (middle) having a thermal conductivity coefficient greater (because of heat from the chip 14) than that of the second portion (sides).
Regarding independent claim 9, Lee et al. teaches a semiconductor chip package, comprising (Fig. 2I):
a lead frame (10) having a first surface (upper surface) and a second surface (lower surface) opposite to each other, with a groove () provided on the first surface of the lead frame (10);
an adhesive (33) filled in the groove;
a semiconductor chip (14) disposed on the adhesive (33) and covering the adhesive (33), wherein a top surface of the semiconductor chip (14) facing away from the adhesive (33) is higher than the first surface of the lead frame (10); and
a carrier (24) provided on the second surface of the lead frame (10) carrying the lead frame (10) and the semiconductor chip (14).
Regarding claim 10, Lee et al. teaches wherein (Fig. 2I), the carrier (24) comprises:
a first portion (middle) overlapping with the semiconductor chip (14); and
a second portion (sides) not overlapping with the semiconductor chip (14), the first portion (middle) having a thermal conductivity coefficient greater (because of heat from the chip 14) than that of the second portion (sides).
Regarding claim 12, Lee et al. teaches wherein (Fig. 2I), a width (d1) of the groove is less than a width (d2) of the semiconductor chip (14).
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Regarding claim 13, Lee et al. teaches wherein (Fig. 2D), a bottom surface of the semiconductor chip (14) facing the adhesive (33) is in contact with the first surface (upper surface) of the lead frame (10).
Regarding independent claim 14, Lee et al. teaches a method for manufacturing a semiconductor chip package, comprising (Figs. 2A-2I):
obtaining a lead frame (10, see Fig. 2A), the lead frame having a first surface (upper surface) and a second surface (lower surface) opposite to each other, with a groove (see Fig. 2B) recessed from the first surface of the lead frame (10) into the lead frame;
completely filling the groove with an adhesive (33, see Fig. 2D); and
disposing a semiconductor chip (14) on the adhesive (33) and covering the adhesive (33), the semiconductor chip (14) being affixed to the lead frame (10) through the adhesive (33) in the groove.
Regarding claim 15, Lee et al. teaches wherein (Fig. 2I), a width (d1) of the groove is less than a width (d2) of the semiconductor chip (14).
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Regarding claim 16, Lee et al. teaches wherein (Fig. 2D), a bottom surface of the semiconductor chip (14) facing the adhesive (33) is in contact with the first surface (upper surface) of the lead frame (10).
Regarding claim 18, Lee et al. teaches wherein (Fig. 2I), the carrier (24) comprises:
a first portion (middle) overlapping with the semiconductor chip (14); and
a second portion (sides), the first portion (middle) having a thermal conductivity coefficient greater (because of heat from the chip 14) than that of the second portion (sides).
Regarding claim 19, Lee et al. teaches wherein (Fig. 2I), further comprising:
removing a portion of the second portion (sides) of the carrier (24) such that the first portion (middle) and the second portion (sides) are not in contact with each other.
Examiner’s Note
12. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
14. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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