DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 7/16/2026 has been entered.
Claims 1 – 26 are pending.
Claims 25 and 26 are newly added.
Claims 1 and 13 have been amended.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 1 is ineligible.
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Step
Analysis
1. Statutory Category?
YES. The claim is directed to a system which falls within the statutory category of a machine.
2A – Prong 1: Judicial Exception Recited?
YES. The claim recites the limitation of “determine aggregate stress for the IC over a time period, based on the oscillation frequency of the ROSC and further based on one or more of: IC voltage, IC temperature, or IC activity”. The limitation of determine aggregate stress falls within the enumerated grouping of mathematical concept of calculation, which can be illustrated from the relevant portion of the spec regarding para [0131]. This limitation, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “a processor, configured to…”, nothing in the claim element precludes the limitation from practically being performed in the mind. For example, but for the “computer-readable encoding of the IC comprising encodings…” language, the claim encompasses a user manually calculating the aggregate stress. The formula does not have to be in the claim to have the limitation directed to an abstract concept. The mere nominal recitation of a generic computer element does not take the claim limitation out of the mental processes grouping. Thus, the claim recites a mental process.
2A – Prong 2: Integrated into a Practical Application?
NO. The claim recites two additional elements: a functional transistor…, and a ring oscillator circuit. The oscillation frequency, IC voltage, IC temperature, or IC activity for obtaining the data is recited at a high level of generality (i.e., as a general means of gathering the data for use in the determination), and amounts to mere data gathering, which is a form of insignificant extra-solution activity. The general processor or program which perform the determination is also recited at a high level of generality, and merely automates the determination. Each of the additional limitations is no more than mere instructions to apply the exception using a generic computer component (the processor/program).
2B: Claim provides an Inventive Concept?
NO. As discussed with respect to Step 2A Prong Two, the additional elements in the claim amounts to no more than mere instructions to apply the exception using a generic computer component.
The same analysis applies here in 2B, i.e., mere instructions to apply an exception using a generic computer component cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. The claim is ineligible.
Dependent Claims(s) 2 – 12 and 25, when analyzed as a whole are held to be ineligible subject matter and are rejected under 35 U.S.C. § 101 because the additional recited limitations(s) fail(s) to establish that the claim is not directed to an abstract idea because the additional limitations(s) are no more than a field of use or merely involve insignificant extra-solution activity as data gathering and calculation.
Particularly:
Regarding Claims 2, 4, 6, 8, 9, 10, and 11, are considered abstract ideas.
Regarding Claims 3, 5, 7, and 12, are considered more than the abstract idea, but not a practical application because they are insignificant pre-solution activity necessary for the abstract idea.
Regarding Claim 25, the claim is considered more than the abstract idea.
Claim 13 is ineligible.
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Step
Analysis
1. Statutory Category?
YES. The claim is directed to a system which falls within the statutory category of a machine.
2A – Prong 1: Judicial Exception Recited?
YES. The claim recites the limitation of “determine aggregate stress for the IC over a time period, based on the oscillation frequency of the ROSC and further based on one or more of: IC voltage, IC temperature, or IC activity”. The limitation of determine aggregate stress falls within the enumerated grouping of mathematical concept of calculation, which can be illustrated from the relevant portion of the spec regarding para [0131]. This limitation, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “a processor, configured to…”, nothing in the claim element precludes the limitation from practically being performed in the mind. For example, but for the “computer-readable encoding of the IC comprising encodings…” language, the claim encompasses a user manually calculating the aggregate stress. The formula does not have to be in the claim to have the limitation directed to an abstract concept. The mere nominal recitation of a generic computer element does not take the claim limitation out of the mental processes grouping. Thus, the claim recites a mental process.
2A – Prong 2: Integrated into a Practical Application?
NO. The claim recites two additional elements: a functional transistor…, and a ring oscillator circuit. The oscillation frequency, IC voltage, IC temperature, or IC activity for obtaining the data is recited at a high level of generality (i.e., as a general means of gathering the data for use in the determination), and amounts to mere data gathering, which is a form of insignificant extra-solution activity. The general processor or program which perform the determination is also recited at a high level of generality, and merely automates the determination. Each of the additional limitations is no more than mere instructions to apply the exception using a generic computer component (the processor/program).
2B: Claim provides an Inventive Concept?
NO. As discussed with respect to Step 2A Prong Two, the additional elements in the claim amounts to no more than mere instructions to apply the exception using a generic computer component.
The same analysis applies here in 2B, i.e., mere instructions to apply an exception using a generic computer component cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. The claim is ineligible.
Dependent Claims(s) 14 – 24 and 26, when analyzed as a whole are held to be ineligible subject matter and are rejected under 35 U.S.C. § 101 because the additional recited limitations(s) fail(s) to establish that the claim is not directed to an abstract idea because the additional limitations(s) are no more than a field of use or merely involve insignificant extra-solution activity as data gathering and calculation.
Particularly:
Regarding Claims 14, 18, and 20 – 23, are considered abstract ideas.
Regarding Claims 15, 16, 17, 19, and 24, are considered more than the abstract idea, but not a practical application because they are insignificant pre-solution activity necessary for the abstract idea.
Regarding Claim 26, the claim is considered more than the abstract idea.
The claims have been considered ineligible under 35 USC 101 by reviewing both the limitations themselves and as ordered combinations of elements which do not amount to a practical application of the abstract limitations.
Comments
The prior art of record found as a result of the search, does not teach alone or in combination all of the elements recited in claims 1 and 13. Therefore, no prior art rejection for claims 1 and 13 is presented in this action. However, Claims 1 – 24 are rejected under 35 U.S.C. 101.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Fayneh et al. (US 12,282,058 B2) suggest an integrated circuit (IC) comprising: a time-to-digital converter (TDC) configured to measure an input-to-output delay of an I/O buffer of a pad the IC, the measured delay reflecting a connection impedance of the pad; and a circuit configured to determine electrical connection integrity of the pad, based on the measurement by the TDC (see claim 1).
Jenkins et al. (US 9,791,500 B2) teaches a method for detecting previous use of a computer chip, the method comprising the steps of: applying a voltage to an array of passive test wires extending between a voltage source and a ground to form a circuit integrated into the computer chip, wherein each passive test wire of the array of test wires is of a different length, width, or thickness, such that each of the passive test wires remains continuous for a different amount of time upon an application of power; measuring the electrical discontinuity of each of the passive test wires to detect previous use of the computer chip; and wherein each of the passive test wires is configured to be activated only by applying power to the computer chip for a specified amount of time, such that the electrical discontinuity occurs only if the computer chip was used for the specified amount of time; the array of passive test wires is coupled to a logic circuit; and the logic circuit is arranged to determine a length of time the computer chip was previously in use based on the current flowing through each of the passive test wires (see claim 1).
Bourstein et al. (US 8,866,501 B2) discloses a method for testing an electronic device, comprising: supplying a first voltage output directly from a voltage regulator to a first power connection terminal of the electronic device via a first conductive path to provide power to the electronic device; providing directly to the voltage regulator a second voltage on a second power connection terminal of the electronic device that is in connection with the first power connection terminal by a first circuit of the electronic device via a second conductive path having a conductivity that is substantially lower than that of the first conductive path; regulating, using the voltage regulator, the first voltage based on a comparison of the second voltage and a target voltage; and determining whether the electronic device meets a performance requirement while the first voltage is regulated (see claim 1).
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/GIOVANNI ASTACIO-OQUENDO/Primary Examiner, Art Unit 2858 8/7/2026
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