DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-11, 13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nourbakhsh et al. (US20230223256) in view of Irsigler et al. (US20130320512).
Regarding claim 1, Nourbakhsh discloses a method of forming a super junction device (paragraph 0035), the method comprising: forming a first N-type material on a substrate (paragraph 0024); etching a trench in the first N-type material, wherein the trench forms at least a first N-type region from the first N-type material (paragraph 0025 and Fig. 3B); causing a sidewall of the trench comprising the first N-type region to form a conformal layer comprising a p-type silicon-containing material to form a P-type region (paragraph 0028 and Fig. 3C); and filling the trench with a second N-type material to form a second N-type region such that the P-type region is between the first N-type region and the second N-type region (paragraph 0034 and Fig. 3G). Nourbakhsh is silent about the conformal layer comprising a P-type silicon-containing material is formed by doping the sidewall of the trench with a P-type dopant. However, Nourbakhsh discloses that the P-type silicon can be formed by any process to produce conformal coverage about the structure (paragraph 0028). In addition, Irsigler teaches that a conformal P-type silicon layer on the sidewall of a trench in N-type silicon can be formed by doping the sidewall of the trench with a P-type dopant (paragraph 0034 and Figs. 2B-2C). Therefore, it would have been obvious to one of ordinary skill, in the art before the effective filing date of the claimed invention, to use a known process for forming a conformal P-type silicon layer on the sidewall of a trench in N-type silicon as taught by Irsigler, in the method of Nourbakhsh, with a reasonable expectation of success. It has been held that combining prior art elements according to known methods to yield predictable results is obvious. See MPEP 2143 I.(A).
Regarding claim 2, Nourbakhsh in view of Irsigler discloses wherein causing the sidewall of the first N-type region in the trench to be doped with the P-type dopant also causes a bottom of the trench to be doped with the P-type dopant (Nourbakhsh, Fig. 3C; Irisigler, paragraph 0034 and Fig. 2C).
Regarding claim 3, Nourbakhsh discloses wherein etching the trench in the first N-type material causes the trench to extend down from a top surface of the first N-type material, and a bottom of the trench comprises at least a portion of the first N-type material between the bottom of the trench and the substrate such that the substrate is not exposed at the bottom of the trench (paragraphs 0024-0025, Fig. 3B).
Regarding claim 4, Nourbakhsh discloses forming a protective oxide layer on the P-type region and a bottom of the trench (paragraph 0030 and Fig. 3D).
Regarding claim 5, Nourbakhsh discloses wherein the protective oxide layer is formed conformally inside of the trench (paragraph 0030 and Fig. 3D). Nourbakhsh is silent about the thickness of the protective oxide. However, Nourbakhsh discloses that the protective oxide layer is formed by oxidizing the conformal P-type silicon layer 330 (paragraph 0030 and Fig. 3D), and layer 330 has a thickness range of about 50 nm or less (paragraph 0028). It would be reasonable to expect that the thickness range of the protective oxide layer in the method of Nourbakhsh would overlap with the range recited in the range recited in the instant claim. Additionally, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation and there is no evidence of the criticality of the claimed range. See MPEP 2144.05II.
Regarding claim 6, Nourbakhsh discloses performing a directional etch downward into the trench to remove a P-doped region at a bottom of the trench without removing the P-type region along the sidewall of the trench (paragraph 0031 and Fig. 3E).
Regarding claim 7, Nourbakhsh discloses wherein the directional etch does not expose a top surface of the substrate at a bottom of the trench (paragraph 0031 and Fig. 3E).
Regarding claim 8, Nourbakhsh discloses forming a protective oxide layer on the P-type region and a bottom of the trench (paragraph 0030 and Fig. 3D).
Regarding claim 9, Nourbakhsh discloses a method of forming a super junction device (paragraph 0035), the method comprising: etching a trench in a first N-type material, wherein the trench forms at least a first N-type region in the first N-type material (paragraphs 0024-0025 and Fig. 3B); forming a P-doped layer on a sidewall of the trench comprising the first N-type region, wherein the P-doped layer comprises a P-type dopant (paragraph 0028 and Fig. 3C); and filling the trench with a second N-type material to form a second N-type region such that the P-type region is between the first N-type region and the second N-type region (paragraph 0034 and Fig. 3G). Nourbakhsh is silent about annealing the P-doped layer sufficiently to cause the P-type dopant to diffuse into the first N-type region, thereby forming a P-type region in the first N-type region. However, Nourbakhsh discloses that the P-type region can be formed by any process to produce conformal coverage about the structure (paragraph 0028). In addition, Irsigler teach that a conformal P-type silicon layer on the sidewall of a trench in N-type silicon can be formed by performing a plasma doping (PLAD) operation on a sidewall of the trench comprising the first N-type region, wherein the PLAD operation dopes the sidewall with a P-type dopant (paragraph 0034 and Figs. 2B-2C); annealing the sidewall sufficiently to cause the P-type dopant to diffuse into the first N-type region, thereby forming a P-type region in the first N-type region (thermal heating reads on annealing, paragraph 0035 and Fig. 2C). Therefore, it would have been obvious to one of ordinary skill, in the art before the effective filing date of the claimed invention, to use a known process for forming the P-type silicon layer on the sidewall of a trench in N-type silicon as taught by Irsigler, in the method of Nourbakhsh, with a reasonable expectation of success. It has been held that combining prior art elements according to known methods to yield predictable results is obvious. See MPEP 2143 I.(A).
Regarding claim 10, Nourbakhsh discloses wherein the P-doped layer comprises boron-doped silicon-containing material formed using a deposition operation (paragraph 0028). Silicon oxide is a common silicon-containing material used in semiconductor device fabrication.
Regarding claim 11, Nourbakhsh discloses Nourbakhsh discloses wherein the P-doped layer comprises boron-doped silicon-containing material formed using a deposition operation (paragraph 0028). Silicon nitride is a common silicon-containing material used in semiconductor device fabrication.
Regarding claim 13, Nourbakhsh discloses wherein the P-doped layer is about 100 nm thick (paragraph 0028).
Regarding claims 15-16, the limitations recited in the “wherein” clauses in the method claims simply expresses the intended results of the recited process; therefore, they are not accorded patentability weight. See MPEP 2111.04.
Regarding claim 17, Nourbakhsh discloses a method of forming a super junction device (paragraph 0035), the method comprising: etching a trench in a first N-type material, wherein the trench forms at least a first N-type region in the first N-type material (paragraphs 0024-0025 and Fig. 3B); forming a conformal layer comprising a p-type silicon-containing material on a sidewall of the trench comprising the first N-type region to form a P-type region (paragraph 0028 and Fig. 3C); and filling the trench with a second N-type material to form a second N-type region such that the P-type region is between the first N-type region and the second N-type region (paragraph 0034 and Fig. 3H). Nourbakhsh is silent about the forming of the P-type region comprising: performing a plasma doping (PLAD) operation on a sidewall of the trench comprising the first N-type region, wherein the PLAD operation dopes the sidewall with a P-type dopant; annealing the sidewall sufficiently to cause the P-type dopant to diffuse into the first N-type region, thereby forming a P-type region in the first N-type region. However, Nourbakhsh discloses that the P-type region can be formed by any process to produce conformal coverage about the structure (paragraph 0028). In addition, Irsigler teach that a conformal P-type silicon layer on the sidewall of a trench in N-type silicon can be formed by performing a plasma doping (PLAD) operation on a sidewall of the trench comprising the first N-type region, wherein the PLAD operation dopes the sidewall with a P-type dopant (paragraph 0034 and Figs. 2B-2C); annealing the sidewall sufficiently to cause the P-type dopant to diffuse into the first N-type region, thereby forming a P-type region in the first N-type region (thermal heating reads on annealing, paragraph 0035 and Fig. 2C). Therefore, it would have been obvious to one of ordinary skill, in the art before the effective filing date of the claimed invention, to use a known process for forming the P-type silicon layer on the sidewall of a trench in N-type silicon as taught by Irsigler, in the method of Nourbakhsh, with a reasonable expectation of success. It has been held that combining prior art elements according to known methods to yield predictable results is obvious. See MPEP 2143 I.(A).
Regarding claim 18, Nourbakhsh discloses wherein a height of the P-type region is greater than or about 70 μm (paragraph 0026, Figs. 3B and 3C).
Regarding claim 19, Nourbakhsh discloses wherein a combined width of the P-type region and the second N-type region is about 4 μm (paragraph 0026, Figs. 3B and 3H).
Regarding claim 20, Nourbakhsh discloses wherein an aspect ratio of an area occupied by second the N-type region and the P-type region is less than or about 20 (paragraph 0026, Figs. 3B and 3H).
Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Nourbakhsh et al. (US20230223256) in view of Irsigler et al. (US20130320512) as applied to claim 9 above, and further in view of Xiao (Introduction to Semiconductor Manufacturing Technology, SPIE Press, 2012, ISBN 978-0-8194-9092-6, pages 150-154).
Regarding claim 12, Nourbakhsh in view of Irsigler is silent about wherein the P-doped layer comprises borophosphosilicate (BPSG) glass. However, Nourbakhsh in view of Irsigler discloses that the P-doped layer is a P-doped junction region (Nourbakhsh, paragraph 0033; Irisigler, paragraph 0035). In addition, Xiao teaches that a P-doped junction region can be formed by depositing a layer of borosilicate (BSG) glass followed by a thermal heating step to drive boron out of the BSG and diffuse boron into silicon (2nd paragraph on page 154). Therefore, it would have been obvious to one of ordinary skill, in the art before the effective filing date of the claimed invention, to use the method of Xiao for forming a P-doped junction region in the method of Nourbakhsh in view of Irsigler, with a reasonable expectation of success. It has been held that substituting equivalents known for the same purpose is obvious. See MPEP 2144.06 II.
Regarding claim 14, Nourbakhsh in view of Irsigler is silent about wherein annealing the doped layer comprises applying a temperature that is between about 700°C and about 1100°C. However, Xiao teaches that annealing temperature of 900°C to 1000°C are known process conditions for forming P-doped junction (1st paragraph 152). Therefore, it would have been obvious to one of ordinary skill, in the art before the effective filing date of the claimed invention, to use known annealing temperatures for forming the P-type junction as taught by Xiao, in the method of Nourbakhsh in view of Irsigler, with a reasonable expectation of success. It has been held that combining prior art elements according to known methods to yield predictable results is obvious. See MPEP 2143 I.(A).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-2, 4, 6, 9-11, 13 and 16 are provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1, 5-7, 9 and 12-13 of copending Application No. 18/630,206 (hereinafter, ‘206).
Regarding claim 1, ‘206 claims discloses a method of forming a super junction device (claim 1), the method comprising: forming a first N-type material on a substrate (claim 1); etching a trench in the first N-type material, wherein the trench forms at least a first N-type region from the first N-type material (claim 1); causing a sidewall of the trench comprising the first N-type region to be doped with a P-type dopant to form a P-type region in the first N-type region (claim 5); and filling the trench with a second N-type material to form a second N-type region such that the P-type region is between the first N-type region and the second N-type region (claim 1).
Regarding claim 2, ‘206 claims wherein causing the sidewall of the first N-type region in the trench to be doped with the P-type dopant also causes a bottom of the trench to be doped with the P-type dopant (claims 1 and 7).
Regarding claim 4, ‘206 claims forming a protective oxide layer on the P-type region and a bottom of the trench (claim 9).
Regarding claim 6, ‘206 claims performing a directional etch downward into the trench to remove a P-doped region at a bottom of the trench without removing the P-type region along the sidewall of the trench (claim 9).
Regarding claim 9, ‘206 claims a method of forming a super junction device (claim 1), the method comprising: etching a trench in a first N-type material on a substrate, wherein the trench forms at least a first N-type region from the first N-type material (claim 1); forming a P-doped layer on a sidewall of the trench comprising the first N-type region, wherein the P-doped layer comprises a P-type dopant (claim 5); annealing the P-doped layer sufficiently to cause the P-type dopant to diffuse into the first N-type region, thereby forming a P-type region in the first N-type region (claim 5); and filling the trench with a second N-type material to form a second N-type region such that the P-type region is between the first N-type region and the second N-type region (claims 1 and 7).
Regarding claim 10, ‘206 claims wherein the P-doped layer comprises boron-doped silicon oxide formed using a deposition operation (claims 5-6).
Regarding claim 11, ‘206 claims wherein the P-doped layer comprises boron-doped silicon nitride formed using a deposition operation (claim 6).
Regarding claim 13, ‘206 claims wherein the P-doped layer is between about 10 nm and 200 nm thick (claim 13), which encompasses the range recited in the instant claim.
Regarding claim 16, ‘206 claims wherein the P-type dopant diffuses into the first N-type region to a concentration of between about 1e16 atoms/cm3 and about 1e18 atoms/cm3 (claim 12).
This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIONG-PING LU whose telephone number is (571) 270-1135. The examiner can normally be reached on M-F: 9:00am – 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua L Allen, can be reached at telephone number (571)270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JIONG-PING LU/
Primary Examiner, Art Unit 1713
Prosecution Insights