DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the claims filled on 8/30/2024 that has been entered, wherein claims 1-3 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/30/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the planned division line" in line 20. There is insufficient antecedent basis for this limitation in the claim. Is the planned division line one of the planned division lines of line 3 or different than the planned division lines? For the purpose of examination, “the planned division line” will be interpreted as “the planned division lines”.
Claims 2 and 3 depend on claim 1 and inherit it deficiencies.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Takeda et al. (US 2014/0334511 A1) in view of Okamoto (JP 2007/090405 A).
Regarding claim 1, Takeda teaches a device chip manufacturing method(Fig. 4) for dividing a wafer(2, ¶0036) into a plurality of chips along a plurality of planned division lines(22, ¶0038) defined on a front surface of the wafer(2, ¶0036), the wafer(2, ¶0036) having a plurality of devices(21, ¶0028) formed at regions sectioned by the planned division lines(22, ¶0038),
the device chip manufacturing method comprising:
forming shield tunnels(23, ¶0038) each having a fine pore(231, ¶0038) and an amorphous region(232, ¶038) surrounding the fine pore(231, ¶0038) along the planned division lines(22, ¶0038), by irradiating the wafer(2, ¶0036) from a back surface side with the laser beam(LB, ¶0038) having a wavelength transmissive to the wafer(2, ¶0036) in a condition in which a focal point(P, ¶0036) of the laser beam(LB, ¶0038) is positioned inside the wafer(2, ¶0036); and
dividing the wafer(2, ¶0036) along the planned division lines(22, ¶0038) where the shield tunnels(23, ¶0038) are formed, by applying an external force(¶0109) to the wafer(2, ¶0036), wherein
forming the shield tunnels(23, ¶0038) includes setting a beam spot(beam diameter), on the front surface(2a) of the wafer(2, ¶0036), of a light of the laser beam(LB, ¶0038) which has passed through the wafer(2, ¶0036) and has reached the front surface of the wafer(2, ¶0036).
Takeda is not relied on to teach setting a beam spot to be equal to or smaller than a width of the planned division lines(22, ¶0038).
Okamoto teaches device chip manufacturing method(Fig. 1-2) wherein a beam spot(spot diameter, ¶0009) to be equal to or smaller(¶0009) than a width of the planned division lines(C, ¶0009). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Takeda, to include forming the shield tunnels includes setting a beam spot, on the front surface of the wafer, of a light of the laser beam which has passed through the wafer and has reached the front surface of the wafer, to be equal to or smaller than a width of the planned division lines, as taught by Okamoto, so that no adhesive is present on the optically effective area, and optical characteristics such as wavefront aberration are not deteriorated(¶0010).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Takeda et al. (US 2014/0334511 A1) and Okamoto (JP 2007/090405 A) as applied to claim 1 above, further in view of Yoshikawa (US 2007/0293021 A) and Sotani et al. (US 2004/0053476 A1).
Regarding claim 2, Takeda, in view of Okamoto, teaches the device chip manufacturing method according to claim 1, wherein forming the shield tunnels(23, ¶0038) includes setting the beam spot(beam diameter), on the front surface of the wafer(2, ¶0036), of the light of the laser beam(LB, ¶0038) which has passed through the wafer(2, ¶0036) and has reached the front surface of the wafer(2, ¶0036).
Takeda and Okamoto are not relied on to teach setting the beam spot(beam diameter) to have an rectangular shape with a major axis along a direction parallel to a direction in which the planned division line extends.
Yoshikawa teaches a device chip manufacturing method(Fig. 11) wherein setting the beam spot(S2) to have an elliptical shape(¶0057, ¶0009) with a major axis(X) along a direction parallel to a direction in which the planned division line(201, ¶0065) extends. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Takeda, so that setting the beam spot to have an elliptical shape with a major axis along a direction parallel to a direction in which the planned division line extends, as taught by Yoshikawa, in order to assure the division of the adhesive film(¶0069).
Takeda, Okamoto and Yoshikawa are not relied on to teach setting the beam spot(beam diameter) to have an rectangular shape.
Sotani teaches a device chip manufacturing method(Fig. 6) wherein setting the beam spot(beam diameter) to have an rectangular shape(Fig. 6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Takeda, so that setting the beam spot to have an rectangular shape, as taught by Sotani, in order to allow crystallization of a wider area as compared with the ellipsoidal beam(¶0063).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Takeda et al. (US 2014/0334511 A1) and Okamoto (JP 2007/090405 A) as applied to claim 1 above, further in view of Yoshikawa (US 2007/0293021 A).
Regarding claim 3, Takeda, in view of Okamoto, teaches the device chip manufacturing method according to claim 1, wherein forming the shield tunnels(23, ¶0038) includes setting the beam spot(beam diameter), on the front surface of the wafer(2, ¶0036), of the light of the laser beam(LB, ¶0038) which has passed through the wafer(2, ¶0036) and has reached the front surface of the wafer(2, ¶0036).
Takeda and Okamoto are not relied on to teach setting the beam spot(beam diameter) to have an elliptical shape with a major axis along a direction parallel to a direction in which the planned division line extends.
Yoshikawa teaches a device chip manufacturing method(Fig. 11) wherein setting the beam spot(S2) to have an elliptical shape(¶0057, ¶0009) with a major axis(X) along a direction parallel to a direction in which the planned division line(201, ¶0065) extends. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Takeda, so that setting the beam spot to have an elliptical shape with a major axis along a direction parallel to a direction in which the planned division line extends, as taught by Yoshikawa, in order to assure the division of the adhesive film(¶0069).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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/LAURA M DYKES/Examiner, Art Unit 2892
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