Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/16/2026, 03/13/2025, and 08/30/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 9, and 12 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yoon et al. (US 20210391407 A1).
Regarding claim 1, Yoon et al. teaches a display device (1) comprising:
a first data line (DLa) and a second data line (DLb) each extending in a first direction (y-direction);
a first voltage line (first initialization voltage line VL1) and a second voltage line (second initialization voltage line VL2) configured to provide different initialization voltages ([0179], Vint1 and Vint2, respectively); and
a plurality of pixels (main sub-pixels Pm), wherein the plurality of pixels include:
a first sub-pixel (left pixel circuit PCa) electrically connected ([0195] and [0178]) to the first data line and the first voltage line and including a first pixel circuit (left pixel circuit PCa) and a first light emitting element (organic light-emitting diode OLED); and \
a second sub-pixel (right pixel circuit PCb) adjacent (FIG.10) to the first sub-pixel, electrically connected ([0195]) to the second data line and the second voltage line, and including a second pixel circuit (right pixel circuit PCb) and a second light emitting element (organic light-emitting diode OLED),
wherein the first voltage line includes a (1-1)-th portion (first vertical voltage line VL1a) extending ([0236]) in the first direction and a (1-2)-th portion (first horizontal voltage line VL1b) electrically connected ([0235]) to the (1-1)-th portion and extending in a second direction (x-direction) intersecting (FIG.10) the first direction, and
wherein the second voltage line includes a (2-1)-th portion (second vertical voltage line VL2a) extending ([0253]) in the first direction and a (2-2)-th portion (second horizontal voltage line VL2b) electrically connected ([0254]) to the (2-1)-th portion and extending (FIG.13) in the second direction.
Regarding claim 2, Yoon et al. teaches the display device of claim 1, wherein
the (1-1)-th portion (first vertical voltage line VL1a) and the (2-1)-th portion (second vertical voltage line VL2a) are in a same layer ([0255], on second interlayer insulating layer 116), and wherein
the (1-1)-th portion (first vertical voltage line VL1a) and the (1-2)-th portion (first horizontal voltage line VL1b) are in different layers ([0269]).
Regarding claim 5, Yoon et al. teaches the display device of claim 1, wherein
the first pixel circuit (left pixel circuit PCa) includes a first driving transistor (first transistor T1) and a (2-1)-th initialization transistor ([0184], fourth transistor T4) connected ([0184]) between a gate electrode (second node N2) of the first driving transistor and the first voltage line (first initialization voltage line VL1), and wherein
the second pixel circuit (right pixel circuit PCb) includes (FIG.10 and [0207]: PCa/PCb with vertical line symmetry) a second driving transistor (corresponding first transistor T1 of right pixel circuit PCb) and a (2-2)-th initialization transistor (corresponding fourth transistor T4 of PCb) connected between a gate electrode (second node N2 of PCb) of the second driving transistor and the second voltage line (second initialization voltage line VL2).
Regarding claim 9, Yoon et al. teaches the display device of claim 1, wherein
each of the first pixel circuit (left pixel circuit PCa) and the second pixel circuit (right pixel circuit PCb) are provided in plurality ([0249]), wherein
the plurality of first pixel circuits are arranged along (FIG.10) the first direction (y-direction), wherein
the plurality of second pixel circuits are arranged along (FIG.10) the first direction (y-direction), and wherein
the plurality of first pixel circuits are respectively spaced (FIG.10) from the plurality of second pixel circuits in the second direction (x-direction).
Regarding claim 12, Yoon et al. teaches the display device of claim 1, wherein the first data line (DLa) and the second data line (DLb) are spaced (FIG.9) from each other in the second direction (x-direction).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 14, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 20210391407 A1) in view of Lee (US 20160321994 A1).
Regarding claim 3, Yoon et al. teaches display device of claim 1. Lee teaches wherein the first and second data lines ([0032], first and second data lines), the (1-1)-th portion ([0032], first initialization voltage line), and the (2-1)-th portion ([0032], second initialization voltage line) are in a same layer ([0021]).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have placed data and voltage line portions of Yoon et al. into same layer as taught by Lee, instead of multilayer layout. Putting the conductive lines on singular layer simplifies the conductive lines layout, thereby providing practicality while maintaining mesh structure of initialization voltage lines extending in both first and second directions, which lowers resistance and increases wiring area, helping deliver initialization voltages more evenly.
Regarding claim 14, Yoon et al. teaches a display device (1) comprising:
a data line (DLa) extending in a first direction (y-direction);
a voltage line (first initialization voltage line VL1) configured to transfer ([0179]) an initialization voltage (first initialization voltage Vint1); and
a pixel (main sub-pixel Pm) electrically connected ([0195]) to the data line and the voltage line, wherein
the pixel includes a pixel circuit (left pixel circuit PCa) and a light emitting element (organic light-emitting diode OLED), wherein
the voltage line includes a first portion (first vertical voltage line VL1a) extending ([0236]) in the first direction and a second portion (first horizontal voltage line VL1b) electrically connected ([0235]) to the first portion and extending in a second direction (x-direction) intersecting (FIG.10) the first direction, and wherein
the first portion and the second portion are in different layers ([0269]).
Yoon et al. does not teach wherein the data line and the first portion are in a same layer.
However, Lee teaches wherein the data line (first data line 171a) and the first portion (initialization voltage line 173) are in a same layer (FIG.5).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have placed data and voltage line portions of Yoon et al. into same layer as taught by Lee, instead of multilayer layout. Putting the conductive lines on singular layer simplifies the conductive lines layout, thereby providing practicality while maintaining mesh structure of initialization voltage lines extending in both first and second directions, which lowers resistance and increases wiring area, helping deliver initialization voltages more evenly.
Regarding claim 16, Yoon et al.in view of Lee teaches display device of claim 14. Yoon et al. teaches wherein the pixel circuit (left pixel circuit PCa) includes:
a driving transistor (first transistor T1); and
a second initialization transistor ([0184], fourth transistor T4) connected ([0184]) between a gate electrode (second node N2) of the driving transistor and the voltage line (first initialization voltage line VL1).
Regarding claim 17, Yoon et al.in view of Lee teaches display device of claim 14. Yoon et al. teaches wherein
the pixel circuit (left pixel circuit PCa) is provided in plurality ([0249]), and wherein
the plurality of pixel circuits (main sub-pixels Pm) are arranged along the first direction (y-direction).
Regarding claim 18, Yoon et al.in view of Lee teaches display device of claim 17. Yoon et al. teaches wherein
the light emitting element (organic light-emitting diode OLED) is provided in plurality ([0087]), and wherein
the plurality of light emitting element are electrically connected ([0087]) to the plurality of pixel circuits (main sub-pixels Pm), respectively.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 20210391407 A1) in view of Kim et al. (US 20220084472 A1).
Regarding claim 4, Yoon et al. teaches the display device of claim 1. Yoon et al. teaches
the second pixel circuit (right pixel circuit PCb) includes a (1-2)-th initialization transistor ([0186], seventh transistor T7) connected between the second voltage line (second initialization voltage line VL2) and the second light emitting element (organic light-emitting diode OLED).
Yoon et al. does not teach wherein the first pixel circuit includes a (1-1)-th initialization transistor connected between the first voltage line and the first light emitting element.
However, Kim et al. teaches wherein the first pixel circuit (pixel 100) includes a (1-1)-th initialization transistor [0073], (seventh transistor T7 as diode initialization transistor) connected between the first voltage line (second initialization voltage VINT2) and the first light emitting element (organic light emitting diode EL).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the left pixel circuit of Yoon et al. to provide the specific arrangement of initialization transistor between initialization voltage line and light emitting element (not node) because this enables each sub-pixel to receive its designated initialization voltage as its light emitting element while retaining separate voltage line architecture of Yoon et al., thereby reducing charge sharing between adjacent pixels and distorted displayed colors.
Claims 6-8, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 20210391407 A1) in view of Kim et al. (US 20220084472 A1) and Lee (US 20160321994 A1).
Regarding claim 6, Yoon et al. teaches the display device of claim 1. Lee et al. teaches further comprising:
a third data line (Dm3); and
a third voltage line (third initialization voltage line Vint3), first voltage line (first initialization voltage line Vint1) and the second voltage line (second initialization voltage line Vint2),
wherein the plurality of pixels (PX) further include
a third pixel (PXG1) adjacent ([0175] and FIG.6) to the second sub-pixel (PXB) and including a third pixel circuit (FIG.6 and [0182]: driving connecting member as core circuit component) and a third light emitting element (organic light-emitting diode (OLED)), and
wherein the third pixel is electrically connected ([0188]) to the third voltage line.
Yoon et al. does not teach a third voltage line configured to provide a voltage different from those of the first voltage line and the second voltage line.
However, Kim et al. teaches a third voltage line (VINT3) configured to provide a voltage different ([0106]) from those of the first voltage line (VINT1) and the second voltage line (VINT2),
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have supplied the third data line of Lee to the 2 sub-pixel/2 voltage line architecture of Yoon et al., and to have supplied the third voltage line of Kim et al., which differs from the first and second voltage lines, to the directional/mesh voltage line arrangement of Yoon et al. Providing a separate third voltage line to third sub-pixel/color allows independent charge paths and thus prevents lateral leakage path between adjacent sub-pixels during driving (that’s usually caused by shared wire) and reduce color deviation or color dragging.
Regarding claim 7, Yoon et al. in view of Kim et al. and Lee teaches the display device of claim 6. Yoon et al. teaches wherein the third voltage line (driving voltage line PL) includes a (3-1)-th portion (driving voltage line PL) extending in the first direction (y-direction, FIG.9 and 11) and a (3-2)-th portion (electrode voltage line HL) electrically connected (through connection electrodes 174) to the (3-1)-th portion and extending in the second direction (x-direction, [0246]).
Regarding claim 8, Yoon et al. in view of Kim et al. and Lee teaches the display device of claim 6. Lee teaches wherein different ([0174]) color data (first, second, third pixels: PXR, PXB, PXG1) are provided to the first to third data lines (first, second, third lines: Dm1, Dm2, Dm3).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have extended the 2 sub-pixel/2 data line architecture of Yoon et al. to also include a third data line and third sub-pixel, as this provides a conventional RGB pixel arrangement while maintaining two direction mesh wiring for lowering resistance and load.
Regarding claim 13, Yoon et al. in view of Kim et al. and Lee teaches the display device of claim 6. Yoon et al. teaches wherein, in a plan view, each of the first voltage line (first initialization voltage lines VL1), the second voltage line (second initialization voltage lines VL2), and the third voltage line (third initialization voltage lines VL3) has a mesh structure ([0235], [0254], and [0246], respectively).
Regarding claim 15, Yoon et al. in view of Lee teaches the display device of claim 14. Yoon et al. does not teach wherein the pixel circuit includes a first initialization transistor connected between the voltage line and the light emitting element.
However, Kim et al. teaches wherein the pixel circuit (pixel 100) includes a first initialization transistor ([0073], seventh transistor T7 as diode initialization transistor) connected between the voltage line (second initialization voltage VINT2) and the light emitting element (organic light emitting diode EL).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the left pixel circuit of Yoon et al. to provide the specific arrangement of initialization transistor between initialization voltage line and light emitting element (not node) because this enables each sub-pixel to receive its designated initialization voltage as its light emitting element while retaining separate voltage line architecture of Yoon et al. as modified by Lee, thereby reducing charge sharing between adjacent pixels and distorted displayed colors.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 20210391407 A1) in view of Park et al. (US 20220310760 A1).
Regarding claim 10, Yoon et al. teaches the display device of claim 9. Yoon et al. teaches
the first light emitting element (organic light-emitting diode OLED) is provided in plurality ([0087]), and
wherein the plurality of first light emitting elements are electrically connected ([0087]) to the plurality of first pixel circuits (left pixel circuit PCa), respectively.
Yoon et al. does not teach wherein, in a plan view, some of the plurality of first light emitting elements overlap the corresponding first pixel circuits, and wherein, in the plan view, the others of the plurality of first light emitting elements do not overlap the corresponding first pixel circuits.
However, Park et al. (US 20220310760 A1) teaches wherein,
in a plan view, some of the plurality of first light emitting elements (first light-emitting element ED1) overlap ([0072]) the corresponding first pixel circuits (first pixel circuit unit PC1), and wherein,
in the plan view, the others of the plurality of first light emitting elements (second light-emitting element ED2) do not overlap ([0091]) the corresponding first pixel circuits (second pixel circuit unit PC2).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to provide the pixel circuit/light emitting element arrangement of Yoon et al. with the specific layout as expressly taught in Park et al. (US 20220310760 A1), as that would allow freedom for different special arrangements within the layout while maintaining shared pixel-circuit arrangement that is beneficial for overall improving display reliability and quality through a more efficient voltage-line layout and pixel organization.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 20210391407 A1) in view of Lee (US 20160321994 A1) and Park et al. (US 20220310760 A1).
Regarding claim 19, Yoon et al. and Lee teach the display device of claim 18. Park et al. (US 20220310760 A1) teaches wherein, in a plan view, some of the plurality of light emitting elements (first light-emitting element ED1) overlap ([0072]) the corresponding pixel circuits (first pixel circuit unit PC1).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to provide the pixel circuit/light emitting element arrangement of Yoon et al. as modified by Lee with the specific layout as expressly taught in Park et al. (US 20220310760 A1), as that would allow freedom for different special arrangements within the layout while maintaining shared pixel-circuit arrangement that is beneficial for overall improving display reliability and quality through a more efficient voltage-line layout and pixel organization.
Regarding claim 20, Yoon et al. and Lee teach the display device of claim 19. Park et al. (US 20220310760 A1) teaches wherein, in the plan view, the others of the plurality of light emitting elements (second light-emitting element ED2) do not overlap ([0091]) the corresponding pixel circuits (second pixel circuit unit PC2).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to provide the pixel circuit/light emitting element arrangement of Yoon et al. as modified by Lee with the specific layout as expressly taught in Park et al. (US 20220310760 A1), as that would allow freedom for different special arrangements within the layout while maintaining shared pixel-circuit arrangement that is beneficial for overall improving display reliability and quality through a more efficient voltage-line layout and pixel organization.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. (US 20210391407 A1) in view of Park et al. (US 20180024392 A1).
Regarding claim 11, Yoon et al. teaches the display device of claim 1. Park et al. (US 20180024392 A1)
teaches wherein, in a plan view, the second data line (second data line DL2) overlaps ([0005] and [0072]) the first light emitting element (first pixel electrode PE1) and does not overlap ([0070]) the second light emitting element (second pixel electrode PE2).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to provide the adjacent sub-pixel/data line arrangement of Yoon et al. with the specific routing relationship taught in Park et al. (US 20180024392 A1) because this provides way of routing second data line through pixel layout while avoiding overlap with second light emitting element region, which contributes to more efficient voltage-line layout and pixel organization and thus overall improved display reliability and quality.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEANNE M KIM whose telephone number is (571)272-8768. The examiner can normally be reached Monday-Thursday 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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