DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 2021/0202502 A1 hereinafter referred to as “Chang”).
With respect to claim 1, Chang discloses, in Figs.1A-21, a semiconductor device, comprising: an inter-metal dielectric (IMD) layer (112, 114-145) on a substrate; and a ferroelectric random access memory (FeRAM) (134) on the ILD layer (see Par.[0023]-[0028] wherein a dielectric layer 144 extends along a top surface of the dielectric layer 112; see Par.[0046] wherein a dielectric layer 145 (may also be referred to as a sacrificial layer) is formed to extend along a top surface of the dielectric layer 144. In some embodiments, the dielectric layer 145 may include SiCN, SiCO, SiO.sub.2, SiN, SiC and AlON, combinations thereof, or other suitable materials; see Par.[0020] wherein the memory region 102A can correspond to an array of memory cells 134 (which may be also referred to as ferroelectric random access memory (FRAM) structures) while the logic device portion 102B can couple logic devices, such as transistors formed in a substrate underlying thereof, to support operation of the memory cells 134), wherein the FeRAM comprises: a first trench (O1) and a second trench (O1) in the IMD layer (112, 144-145); a bottom electrode (136) in the first trench (O1) and the second trench (O1) and extending to a surface of the IMD layer (112, 114-145); a ferroelectric (FE) layer on the bottom electrode; and a top electrode on the FE layer (see Par.[0049]-[0050] wherein with reference to FIG. 7, one or more etching processes are performed to form an opening O1 exposing the bottom conductive line 106 of the memory region 102A using the patterned mask 147 as an etching mask, while the dielectric layers 144 and 145 of the logic region 102B remains, and the patterned mask layer 147 is removed after the etching; the width W3 of the opening O1 is less than the width W1 of the bottom conductive line 106 when view from a cross section taken along the second direction; with reference to FIG. 8, a bottom electrode layer 136 is conformally formed over the dielectric layers 144 and 145 and the bottom conductive line 106. Specifically, the bottom electrode layer 136 lines a sidewall of the opening O1 and top surfaces of the bottom conductive line 106 and the dielectric layer 145; see Par.[0036]-[0038], [0040], [0054]-[0058] wherein the top electrode layer 156 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials).
With respect to claim 2, Chang discloses, in Figs.1A-21, the semiconductor device, further comprising: a hard mask (152) on the FeRAM (134); a second IMD layer (112, 144-145) on the hard mask (152) (see Par.[0039] wherein the IMD layer 152 is formed over the protective liner layer 150 and fills a gap between two neighboring memory cells 134 as shown in FIG. 1B); and a first metal interconnection (154, 158) and a second metal interconnection (153, 157, 106) in the second IMD layer (112, 144-145) (see Par.[0021]-[0022] wherein the top electrode via (TEVA) 154 and the conductive line 158 may land on a periphery of cell line and non-overlaps the memory cell 134, such that the top electrode via 154 may not align the memory cell 134 so as to improve the process window; see Par.[0062] wherein a metal material (e.g., copper, aluminum, etc) is filled in the openings O2 and O3 by suitable processes such as plating, chemical vapor deposition (CVD), physical vapor deposition (PVD) and/or the like, and then removing the conductive material layer above the upper IMD layer 152 by suitable processes such as CMP, etching and/or the like to form the top electrode via 154 of the memory region 102A and the top electrode via 153 of the logic region 102B; then, the conductive line 158 is formed above the top electrode via 154, and the conductive line 157 is formed above the top electrode via 153; the top electrode vias 153 and 154 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials. In some embodiments, the conductive lines 157 and 158 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials; see Par.[0024]-[0025] wherein the bottom conductive line 106 is embedded in the dielectric layer 112. In some embodiments, the bottom conductive line 106 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials; see Par.[0055]-[0056] wherein a patterned mask layer 157 is formed over the top electrode layer 156 and patterned to form separated mask portions; the patterned mask layer 157 covers portions of the memory region 102A (See FIGS. 13B and 13C) and exposes the logic device portion 102B (See FIG. 13A); the patterned mask layer 157 exposes entirety of the logic device portion 102B; see Par.[0040] wherein a conductive line 158 embedded in the IMD layer 152 and extending along the first direction (see FIG. 1B); the ferroelectric layer 138 of the memory cell 134 extends across the conductive line 158; the top electrode layer 156 of the memory cell 134 extends across the conductive line 158).
With respect to claim 3, Chang discloses, in Figs.1A-21, the semiconductor device, wherein the hard mask is on the bottom electrode and the top electrode (see Par.[0021]-[0022] wherein the top electrode via (TEVA) 154 and the conductive line 158 may land on a periphery of cell line and non-overlaps the memory cell 134, such that the top electrode via 154 may not align the memory cell 134 so as to improve the process window; see Par.[0062] wherein a metal material (e.g., copper, aluminum, etc) is filled in the openings O2 and O3 by suitable processes such as plating, chemical vapor deposition (CVD), physical vapor deposition (PVD) and/or the like, and then removing the conductive material layer above the upper IMD layer 152 by suitable processes such as CMP, etching and/or the like to form the top electrode via 154 of the memory region 102A and the top electrode via 153 of the logic region 102B; then, the conductive line 158 is formed above the top electrode via 154, and the conductive line 157 is formed above the top electrode via 153; the top electrode vias 153 and 154 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials. In some embodiments, the conductive lines 157 and 158 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials; see Par.[0024]-[0025] wherein the bottom conductive line 106 is embedded in the dielectric layer 112. In some embodiments, the bottom conductive line 106 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials; see Par.[0055]-[0056] wherein a patterned mask layer 157 is formed over the top electrode layer 156 and patterned to form separated mask portions; the patterned mask layer 157 covers portions of the memory region 102A (See FIGS. 13B and 13C) and exposes the logic device portion 102B (See FIG. 13A); the patterned mask layer 157 exposes entirety of the logic device portion 102B; see Par.[0040] wherein a conductive line 158 embedded in the IMD layer 152 and extending along the first direction (see FIG. 1B); the ferroelectric layer 138 of the memory cell 134 extends across the conductive line 158; the top electrode layer 156 of the memory cell 134 extends across the conductive line 158).
With respect to claim 4, Chang discloses, in Figs.1A-21, the semiconductor device, wherein the first metal interconnection connects the top electrode (see Par.[0021]-[0022] wherein the top electrode via (TEVA) 154 and the conductive line 158 may land on a periphery of cell line and non-overlaps the memory cell 134, such that the top electrode via 154 may not align the memory cell 134 so as to improve the process window; see Par.[0062] wherein a metal material (e.g., copper, aluminum, etc) is filled in the openings O2 and O3 by suitable processes such as plating, chemical vapor deposition (CVD), physical vapor deposition (PVD) and/or the like, and then removing the conductive material layer above the upper IMD layer 152 by suitable processes such as CMP, etching and/or the like to form the top electrode via 154 of the memory region 102A and the top electrode via 153 of the logic region 102B; then, the conductive line 158 is formed above the top electrode via 154, and the conductive line 157 is formed above the top electrode via 153; the top electrode vias 153 and 154 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials. In some embodiments, the conductive lines 157 and 158 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials; see Par.[0024]-[0025] wherein the bottom conductive line 106 is embedded in the dielectric layer 112. In some embodiments, the bottom conductive line 106 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials; see Par.[0055]-[0056] wherein a patterned mask layer 157 is formed over the top electrode layer 156 and patterned to form separated mask portions; the patterned mask layer 157 covers portions of the memory region 102A (See FIGS. 13B and 13C) and exposes the logic device portion 102B (See FIG. 13A); the patterned mask layer 157 exposes entirety of the logic device portion 102B; see Par.[0040] wherein a conductive line 158 embedded in the IMD layer 152 and extending along the first direction (see FIG. 1B); the ferroelectric layer 138 of the memory cell 134 extends across the conductive line 158; the top electrode layer 156 of the memory cell 134 extends across the conductive line 158).
With respect to claim 5, Chang discloses, in Figs.1A-21, the semiconductor device, wherein the second metal interconnection connects the bottom electrode (see Par.[0021]-[0022] wherein the top electrode via (TEVA) 154 and the conductive line 158 may land on a periphery of cell line and non-overlaps the memory cell 134, such that the top electrode via 154 may not align the memory cell 134 so as to improve the process window; see Par.[0062] wherein a metal material (e.g., copper, aluminum, etc) is filled in the openings O2 and O3 by suitable processes such as plating, chemical vapor deposition (CVD), physical vapor deposition (PVD) and/or the like, and then removing the conductive material layer above the upper IMD layer 152 by suitable processes such as CMP, etching and/or the like to form the top electrode via 154 of the memory region 102A and the top electrode via 153 of the logic region 102B; then, the conductive line 158 is formed above the top electrode via 154, and the conductive line 157 is formed above the top electrode via 153; the top electrode vias 153 and 154 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials. In some embodiments, the conductive lines 157 and 158 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials; see Par.[0024]-[0025] wherein the bottom conductive line 106 is embedded in the dielectric layer 112. In some embodiments, the bottom conductive line 106 may include copper, Pt, Ru, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), combinations thereof, or other suitable materials; see Par.[0055]-[0056] wherein a patterned mask layer 157 is formed over the top electrode layer 156 and patterned to form separated mask portions; the patterned mask layer 157 covers portions of the memory region 102A (See FIGS. 13B and 13C) and exposes the logic device portion 102B (See FIG. 13A); the patterned mask layer 157 exposes entirety of the logic device portion 102B; see Par.[0040] wherein a conductive line 158 embedded in the IMD layer 152 and extending along the first direction (see FIG. 1B); the ferroelectric layer 138 of the memory cell 134 extends across the conductive line 158; the top electrode layer 156 of the memory cell 134 extends across the conductive line 158).
With respect to claim 6, Chang discloses, in Figs.1A-21, the semiconductor device, wherein a sidewall of the top electrode is aligned with a sidewall of the FE layer (see Fig.19).
Citation of Pertinent Prior Art
The prior art made of record (e.g., see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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