DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-12 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. (US 9330997 B1).
Re Claim 1, Lim teaches an electronic package (Figs. 1A-1C), comprising:
a carrier structure (120, Fig. 1A, Col 2, lines 50-55);
a first electronic component (110, Fig. 1A, Col 2, lines 50-55) disposed on the carrier structure (120); and
a thermal conductive layer (135+136+127, Figs. 1A-1B, Col 4, lines 12-20 and 42-25) contacting and covering the first electronic component (110, Fig. 1A, Col 3, lines 60-65) and the carrier structure (120, Fig. 1A).
Re Claim 2, Lim teaches the electronic package of claim 1, wherein the carrier structure (120) has a first surface (top surface of 120, Fig. 1A) and a second surface (bottom surface of 120, Fig. 1A) opposite to the first surface, and a primary component connection area (marked “primary area” in annotated Fig. 1A, below) and a secondary component connection area (marked “secondary area” in annotated Fig. 1A, below) are defined on the first surface (top surface of 120).
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Re Claim 3, Lim teaches the electronic package of claim 2, wherein the first electronic component (110, Fig. 1A) has an active surface (bottom surface of 110) and a non-active surface (top surface of 110) opposite to the active surface, and the first electronic component (110) is disposed through the active surface (bottom surface of 110) thereof in the primary component connection area of the carrier structure (“primary area” of 120) via a plurality of conductive bumps (115, Fig. 1A, Col 3, lines 13-17).
Re Claim 5, Lim teaches the electronic package of claim 3, wherein the thermal conductive layer (135+136+127, Fig. 1A) contacts and covers the non-active surface of the first electronic component (top surface of 110, see Fig. 1A).
Re Claim 6, Lim teaches the electronic package of claim 2, further comprising a second electronic component (140, Fig. 1A, Col 3, lines 45-50) disposed in the secondary component connection area of the carrier structure (“secondary area” of 120).
Re Claim 7, Lim teaches the electronic package of claim 6, wherein the thermal conductive layer (135+136+127, Figs. 1A-1B) is formed with an opening (open slots 145, Fig. 1B, Col 4, lines 46-60) exposing the second electronic component (140, see Fig. 1B).
Re Claim 8, Lim teaches the electronic package of claim 6, wherein the second electronic component (140, Fig. 1A) is a passive component (140 can be a passive component, Col 3, lines 45-50).
Re Claim 9, Lim teaches the electronic package of claim 2, further comprising a plurality of conductive components (126, Fig. 1A, Col 3, lines 19-26) implanted on the second surface of the carrier structure (bottom surface of 120, Fig. 1A).
Re Claim 10, Lim teaches the electronic package of claim 1, wherein the thermal conductive layer (135+136+127, Fig. 1A) contacts and covers the first electronic component (110, Fig. 1A) and the carrier structure (120, Fig. 1A) by coating a metal layer with a high thermal conductivity (135+136 may be made of copper and thermally contacts 110 and 120, Col 4, lines 8-20).
Re Claim 11, Lim teaches the electronic package of claim 1, wherein the thermal conductive layer (135+136+127, Figs. 1A-1B) is defined with a first area (135, Figs. 1A-1B) and a second area (136+127, Figs. 1A-1B), the first area (135) corresponds to an area on the carrier structure where the first electronic component is disposed (135 corresponds to an area where 110 is disposed, see Figs. 1A-1B), and the second area (136+127) corresponds to an area of the carrier structure where the first electronic component is not disposed (136+127 corresponds to an area where 110 is not disposed, see Figs. 1A-1B).
Re Claim 12, Lim teaches the electronic package of claim 11, wherein a thickness of the thermal conductive layer in the first area (marked “t1” in annotated Fig. 1A below) is smaller than a thickness of the thermal conductive layer in the second area (marked “t2” in annotated Fig. 1A below, where “t1” is smaller than “t2”).
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Re Claim 14, Lim teaches the electronic package of claim 11, wherein a material of the thermal conductive layer located in the first area (135 can be made of copper, Col 4, lines 8-20) is different from a material of the thermal conductive layer located in the second area (136+127 contains an adhesive layer 127, which is different from the copper material of 135, Col 4, lines 12-20 and 42-25).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 9330997 B1), and further in view of Ng et al. (US 2021/0066883 A1).
Re Claim 4, Lim teaches the electronic package of claim 3, but does not disclose an underfill formed between the carrier structure and the first electronic component to cover the plurality of conductive bumps.
Related art Ng teaches a similar semiconductor device which further comprises an underfill (31, Fig. 3, para [0065]) formed between the carrier structure (30, Fig. 3) and the first electronic component (32, Fig. 3) to cover the plurality of conductive bumps (320, Fig. 3).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to include an underfill into the device of Lim formed between the chip and the carrier substrate, and covering the conductive bumps, as taught by Ng, because the underfill protects the conductive bumps from mechanical and thermal stress.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 9330997 B1).
Re Claim 13, Lim teaches the electronic package of claim 11, but does not explicitly disclose that the ratio of the thickness of the thermal conductive layer in the first area (135, Fig. 1A) to the thickness of the thermal conductive layer in the second area (136+127, Fig. 1A) is 1:10.
Lim discloses that the ratio of the thickness of the thermal conductive layer in the first area (135, marked “t1” in annotated Fig. 1A below) to the thickness of the thermal conductive layer in the second area (136+127, marked “t2” in annotated Fig. 1A below Fig. 1A) is approximately 1:3. Lim further discloses that the thermal conducting layer should have a profile such that it has thick edges and thinner middle portion (Col 8, lines 1-4) for efficient thermal conduction. Thus, it would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the ratio of the thicknesses to obtain optimal thermal management of the device, depending on the shape and sizes of the active and passive components and arrive at the claimed limitation. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed thickness ratio would have been obvious to one of ordinary skill in the art.
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Rejection 2
Claim Rejections - 35 USC § 102
Claims 1-3, 5-9 and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao et al. (US 2017/0077039 A1).
Re Claim 1, Liao teaches an electronic package (Fig. 17G), comprising:
a carrier structure (100, Fig. 17G, para [0109]);
a first electronic component (111, Fig. 17G, para [0110]) disposed on the carrier structure (100); and
a thermal conductive layer (113, Fig. 17G, para [0113]) contacting and covering the first electronic component (111) and the carrier structure (100).
Re Claim 2, Liao teaches the electronic package of claim 1, wherein the carrier structure (100) has a first surface (top surface of 100, Fig. 17G) and a second surface (bottom surface of 100, Fig. 17G) opposite to the first surface, and a primary component connection area (marked “primary area” in annotated Fig. 17G, below) and a secondary component connection area (marked “secondary area” in annotated Fig. 17G, below) are defined on the first surface (top surface of 100).
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Re Claim 3, Liao teaches the electronic package of claim 2, wherein the first electronic component (111, Fig. 17G) has an active surface (bottom surface of 111) and a non-active surface (top surface of 111) opposite to the active surface, and the first electronic component (111) is disposed through the active surface (bottom surface of 111) thereof in the primary component connection area of the carrier structure (“primary area” of 100) via a plurality of conductive bumps (marked “bumps” in annotated Fig. 17G above).
Re Claim 5, Liao teaches the electronic package of claim 3, wherein the thermal conductive layer (113, Fig. 17G) contacts and covers the non-active surface of the first electronic component (top surface of 111, see Fig. 17G).
Re Claim 6, Liao teaches the electronic package of claim 2, further comprising a second electronic component (147, Fig. 17G, para [0111]) disposed in the secondary component connection area of the carrier structure (“secondary area” of 100).
Re Claim 7, Liao teaches the electronic package of claim 6, wherein the thermal conductive layer (113, Fig. 17G) is formed with an opening (opening 147h, Fig. 17G, para [0114]) exposing the second electronic component (147, see Fig. 17G).
Re Claim 8, Liao teaches the electronic package of claim 6, wherein the second electronic component (147, Fig. 17G) is a passive component (147 can be a passive component, para [0111]).
Re Claim 9, Liao teaches the electronic package of claim 2, further comprising a plurality of conductive components implanted on the second surface of the carrier structure (plurality of conductive pads on the bottom surface of 100, Fig. 17G).
Re Claim 11, Liao teaches the electronic package of claim 1, wherein the thermal conductive layer (113, Fig. 17G) is defined with a first area (marked “1st area” in annotated Fig. 17G below) and a second area (marked “2nd area” in annotated Fig. 17G below), the first area corresponds to an area on the carrier structure where the first electronic component (111) is disposed (see Fig. 17G), and the second area corresponds to an area of the carrier structure where the first electronic component is not disposed (see Fig. 17G).
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Re Claim 12, Liao teaches the electronic package of claim 11, wherein a thickness of the thermal conductive layer in the first area (marked “thickness1” in annotated Fig. 17G above) is smaller than a thickness of the thermal conductive layer in the second area (marked “thickness2” in annotated Fig. 17G above, where “thickness1” is smaller than “thickness2”).
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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