DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Status of the Application
1. Acknowledgement is made of the amendment & Terminal Disclaimer received on 11/2/2025. Claims 1-20 are pending in this application.
Information Disclosure Statement
2. Applicant is suggested/reminded to disclose relevant prior art(s) or other information that may be material to the patentability of the invention in a pending application. The prior art information must be submitted in the form of an Information Disclosure Statement (“IDS”) (see MPEP 609 & 2001 and 37 CFR 1.56).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In particular, claims 1, 8 & 15, each cites “wherein said first metal layers are disposed above and/or below said first level; a first oxide layer disposed atop of said first level, wherein said first oxide laver comprises at least one thru laver via, and wherein said at least one thru layer via comprises a metal” is not clear when considering said first metal layers are below said first level. It is not clear because the claims do not clearly specify any particular connection/relationship between at least one thru layer via & first transistors when said first metal layer are below said first level. In the other hand, when consider said firs metal layers are above said first level, it is not clear because there is no any particular connection specified between at least one thru layer via & said first metal layers.
Further, claims 1, 8 & 15, each cites “a second level comprising second transistors, at least one second metal layer” is not clear, because the claims do not clearly specify any particular connection & position between second transistors & at least one second metal layer within the formed device.
Applicant is suggested to revise and clarify the claim(s) to avoid any further confusions.
For best understanding and examination purpose, the claim(s) will be best considered based on drawings, disclosure, and/or any applicable prior arts.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 2, 4, 6 and 7 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Park (US 2006/0146233) in view of Fung (US 7,804,130).
Re claim 1, Park teaches, under BRI, Fig. 3 & 4C, claims 3 & 4, [0021, 0033, 0034, 0045, 0070], a 3D semiconductor device, the device comprising:
-a first level (200, 203) comprising a first single crystal layer, said first level comprising first transistors (201, 202), wherein each of said first transistors comprises a single crystal channel (e.g., based on single crystal silicon substrate);
-first metal layers (204A, 206A-B, 207) interconnecting at least said first transistors,
wherein said first metal layers (204A, 206A-B, 207) are disposed above and/or below said first level (200, 203);
-a first oxide layer (205) (e.g., oxide based layer) disposed atop of said first level (200, 203),
wherein said first oxide layer (205) comprises at least one thru layer via (206C), and
wherein said at least one thru layer via (206C) comprises a metal;
-a second level (102, 108, 110) comprising second transistors (Tx), at least one second metal layer (109, 111A-C), and at least one array of memory cells (e.g., based on plurality of transistors),
wherein each of said memory cells comprises at least one of said second transistors (e.g., plurality of transistors),
wherein said second level (102, 108, 110) overlays said first oxide layer (205), wherein said at least one of said second transistors (Tx) comprises a recessed channel, and
wherein said second level (102, 108, 110) is directly bonded to said first level (200, 203).
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Park does not teach said at least one of said second transistors comprises a recessed channel.
Fung teaches said at least one of said second transistors comprises a recessed channel (Fig. 4, col. 1, lines 40-50).
As taught by Fung, one of ordinary skill in the art would utilize & modify the above teaching into Park to obtain recessed channel as claimed, because it aids in increasing the effective channel length that improves the short channel effect.
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was made to employ the teaching as taught by Fung in combination with Park due to above reason.
Re claim 2, Park teaches said first level comprises control of power delivery (as intended use) to said second level.
Re claim 4, Park teaches said first level comprises control of data (as intended use) written on said memory cells.
Re claim 6, Park teaches, under BRI, Fig. 3, said bonded comprises direct metal-to-metal bonds (between 111 & 206).
Re claim 7, Park teaches said second level comprises a second single crystal layer (e.g., based on single crystal silicon substrate) [0070].
5. Claim 3 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Park as modified by Fung as applied to claim 1 above, and further in view of Schrinsky (US 2010/0120246).
The teachings of Park/Fung have been discussed above.
Re claim 3, Park/Fung does not teach said second level comprises a plurality of DRAM memory cells.
Schrinsky teaches “The transistors may be part of a memory array, such as a dynamic random access memory (DRAM) array” [0015].
As taught by Schrinsky, one of ordinary skill in the art would utilize the above teaching to obtain said second level comprises a plurality of DRAM memory cells as claimed, because DRAM memory cells are known in the art, and it aids in achieving desired integrated structure with increased density.
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was made to employ the teaching as taught by Schrinsky in combination with Park/Fung due to above reason.
6. Claim 5 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Park as modified by Fung as applied to claim 1 above, and further in view of Hayashi et al. (US 4,980,308).
The teachings of Park/Fung have been discussed above.
Re claim 5, Park/Fung does not teach said at least one of said second transistors comprises a double-sided-gate.
Hayashi teaches a double-side gate type MIS semiconductor device (col. 2, lines 33-35).
As taught by Hayashi, one of ordinary skill in the art would utilize the above teaching to obtain said at least one of said second transistors comprises a double-sided-gate as claimed, because it aids in improving the effective carrier mobility of a formed device.
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was made to employ the teaching as taught by Hayashi in combination with Park/Fung due to above reason.
7. Claims 8, 9, 13 and 14 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Park (US 2006/0146233) in view of Schrinsky (US 2010/0120246).
Re claim 8, Park teaches, under BRI, Fig. 3 & 4C, claims 3 & 4, [0021, 0033, 0045, 0070], a 3D semiconductor device, the device comprising:
-a first level (200, 203) comprising a first single crystal layer, said first level comprising first transistors (201, 202), wherein each of said first transistors comprises a single crystal channel (e.g., based on single crystal silicon substrate);
-first metal layers (204A) interconnecting at least said first transistors;
wherein said first metal layers (204A, 206A-B, 207) are disposed above and/or below said first level (200, 203);
-a first oxide layer (205) (e.g., oxide based layer) disposed atop of said first level (200, 203),
wherein said first oxide layer (205) comprises at least one thru layer via (206C), and
wherein said at least one thru layer via (206C) comprises a metal;
-a second level (102, 108, 110) comprising second transistors (Tx), at least one second meta layers (109, 111A-C), and at least one array of memory cells (e.g., based on plurality of transistors),
wherein each of said memory cells comprises at least one of said second transistors (e.g., plurality of transistors),
wherein said second level (102, 108, 110) overlays said first oxide layer (205), and
wherein said second level (102, 108, 110) is directly bonded to said first level (200, 203).
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Park does not teach said memory cells are DRAM type memory cells.
Schrinsky teaches “The transistors may be part of a memory array, such as a dynamic random access memory (DRAM) array” [0015].
As taught by Schrinsky, one of ordinary skill in the art would utilize the above teaching to obtain DRAM type memory cells as claimed, because DRAM memory cells are known in the art, and it aids in achieving desired integrated structure with increased density.
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was made to employ the teaching as taught by Schrinsky in combination with Park due to above reason.
Re claim 9, Park teaches said first level comprises control of power delivery (as intended use) to said second level.
Re claim 13, Park teaches, under BRI, Fig. 3, said bonded comprises direct metal-to-metal bonds (between 111 & 206).
Re claim 14, Park teaches said second level comprises a second single crystal layer (e.g., based on single crystal silicon substrate) [0070].
8. Claims 10 and 11 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Park as modified by Schrinsky as applied to claim 8 above, and further in view of Fung (US 7,804,130).
The teachings of Park/Schrinsky have been discussed above
Re claim 10, Park/Schrinky does not teach said at least one of said second transistors comprises a recessed channel.
Fung teaches said at least one of said second transistors comprises a recessed channel (col. 1, lines 40-50).
As taught by Fung, one of ordinary skill in the art would utilize & modify the above teaching into Park to obtain recessed channel as claimed, because it aids in increasing the effective channel length that improves the short channel effect.
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was made to employ the teaching as taught by Fung in combination with Park/Schrinsky due to above reason.
Re claim 11, in combination cited above, Fung teaches said at least one of said second transistors has a gate oxide comprising hafnium oxide (col. 4, 4th par.).
9. Claim 12 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Park as modified by Schrinsky as applied to claim 8 above, and further in view of Hayashi et al. (US 4,980,308).
The teachings of Park/Schrinsky have been discussed above.
Re claim 5, Park/Schrinsky does not teach said at least one of said second transistors comprises a double-sided-gate.
Hayashi teaches a double-side gate type MIS semiconductor device (col. 2, lines 33-35).
As taught by Hayashi, one of ordinary skill in the art would utilize the above teaching to obtain said at least one of said second transistors comprises a double-sided-gate as claimed, because it aids in improving the effective carrier mobility of a formed device.
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was made to employ the teaching as taught by Hayashi in combination with Park/Schrinsky due to above reason.
10. Claims 15, 16, 19 and 20 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Park (US 2006/0146233) in view of Schrinsky (US 2010/0120246) and Kitabatake et al. (US 2006/0055027).
Re claim 15, Park teaches, under BRI, Fig. 3 & 4C, claims 3 & 4, [0021, 0033, 0045, 0070], a 3D semiconductor device, the device comprising:
-a first level (200, 203) comprising a first single crystal layer, said first level comprising first transistors (201, 202), wherein each of said first transistors comprises a single crystal channel (e.g., based on single crystal silicon substrate);
-first metal layers (204A) interconnecting at least said first transistors;
wherein said first metal layers (204A, 206A-B, 207) are disposed above and/or below said first level (200, 203);
-a first oxide layer (205) (e.g., oxide based layer) disposed atop of said first level (200, 203),
wherein said first oxide layer (205) comprises at least one thru layer via (206C), and
wherein said at least one thru layer via (206C) comprises a metal;
-a second level (102, 108, 110) comprising second transistors (Tx), at least one second metal layer (109, 111A-C), and at least one array of memory cells (e.g., based on plurality of transistors),
wherein each of said memory cells comprises at least one of said second transistors (e.g., plurality of transistors), and
wherein said second level (102, 108, 110) overlays said oxide layer (205).
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Park does not teach said memory cells are DRAM type memory cells.
Schrinsky teaches “The transistors may be part of a memory array, such as a dynamic random access memory (DRAM) array” [0015].
As taught by Schrinsky, one of ordinary skill in the art would utilize the above teaching to obtain DRAM type memory cells as claimed, because DRAM memory cells are known in the art, and it aids in achieving desired integrated structure with increased density.
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was made to employ the teaching as taught by Schrinsky in combination with Park due to above reason.
Park/Schrinsky does not explicitly teach a heat removal path from said second transistors to an external surface of said device.
Kitabatake teaches, Fig. 8, [0113], a heat removal path (66) from said second transistors (TR1) to an external surface of said device.
As taught by Kitabatake, one of ordinary skill in the art would utilize & modify the above teachings to obtain a heat removal path from said second transistors to an external surface of said device as claimed, because it aids in improving heat dissipation and the operation efficiency.
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was made to employ the teaching as taught by Kitabatake in combination with Park/Schrinsky due to above reason.
Re claim 16, Park teaches said first level comprises control of power delivery (as intended use) to said second level.
Re claim 19, Park teaches, under BRI, Fig. 3, said bonded comprises direct metal-to-metal bonds (between 111 & 206).
Re claim 20, Park teaches said second level comprises a second single crystal layer (e.g., based on single crystal silicon substrate) [0070].
11. Claims 17 and 18 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Park as modified by Schrinsky/Kitabatake as applied to claim 15 above, and further in view of Fung (US 7,804,130).
The teachings of Park/Schrinsky/Kitabatake have been discussed above
Re claim 17, Park/Schrinky/Kitabatake does not teach said at least one of said second transistors comprises a recessed channel.
Fung teaches said at least one of said second transistors comprises a recessed channel (col. 1, lines 40-50).
As taught by Fung, one of ordinary skill in the art would utilize & modify the above teaching into Park to obtain recessed channel as claimed, because it aids in increasing the effective channel length that improves the short channel effect.
Thus, it would have been obvious to one of ordinary skill in the art at the time the invention was made to employ the teaching as taught by Fung in combination with Park/Schrinsky/Kitabatake due to above reason.
Re claim 18, in combination cited above, Fung teaches said at least one of said second transistors has a gate oxide comprising hafnium oxide (col. 4, 4th par.).
Response to Arguments
12. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
The claims are amended including newly added features, interpretation & rejection under the cited prior arts are also changed to meet the newly added features. In further consideration, Park teaches, under BRI, Fig. 3 teaches wherein said first metal layers (204A, 206A-B, 207) are disposed above and/or below said first level (200, 203), a first oxide layer (205) (e.g., oxide based layer) disposed atop of said first level (200, 203), wherein said first oxide layer (205) comprises at least one thru layer via (206C), and wherein said at least one thru layer via (206C) comprises a metal; a second level (102, 108, 110) comprising second transistors (Tx), at least one second metal layer (109, 111A-C), and at least one array of memory cells (e.g., based on plurality of transistors).
Fung, in the other hand, teaches at least of said second transistors comprises a recess channel. It is easily recognized by a skill person in the art, both references are direct to transistor structure. Hence, one of ordinary skill in the art would have been motivated to combine Park and Fung to arrive the claimed invention.
Schrinsky, in the other hand, teaches said memory cells are DRAM type memory cells [0015]. It is easily recognized by a skill person in the art that transistors are known features of a memory array, and DRAM type memory is known in the art. Hence, one of ordinary skill in the art would have been motivated to combine Park and Schinsky to arrive the claimed invention.
Kitabatake (new cited reference) teaches, Fig. 8, [0113], heat removal path (66) from said second transitors (TR1) to an external surface of said device. In order to improving heat dissipation & operation efficiency, one of ordinary skill in the art would have motivated to combine Park, Schrinsky & Kitabatake to arrive the claimed invention.
Under BRI, given a broadest reasonable interpretation, Park, Fung, Schinsky and Kitabatake meet the claimed invention. Details included in the above rejection.
Conclusion
13. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 11/10/25