DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0168599 to Udrea et al. (cited in IDS of 09/09/2024, hereinafter Udrea) in view of Lin et al. (US 2020/0105741, hereinafter Lin).
With respect to Claim 1, Udrea discloses a method of manufacturing a resistor-transistor-logic circuit (e.g., high-voltage GaN device, low-voltage GaN device, and high value resistor integrated on the same substrate) (Udrea, Figs. 2, 15, 19, 21(a)-21(b), ¶0001, ¶0018-¶0035, ¶0114-¶0026, ¶0142, ¶0145, ¶0147-¶0148) with GaN structures, comprising:
providing a substrate (4) (Udrea, Figs. 2, 15, 19, 21(a)-21(b), ¶0114-¶0115, ¶0118, ¶0147-¶0148) with a high-voltage device region (205), a low-voltage device region (210/215) and a resistor region (32);
sequentially forming a GaN layer (2/3) (Udrea, Figs. 2, 15, 19, 21(a)-21(b), ¶0115, ¶0119-¶0120, ¶0147-¶0148), an AlGaN barrier layer (1) and a p-type doped GaN capping layer (14) on said substrate (4);
patterning (e.g., removing section of pGaN layer 14) (Udrea, Figs. 21(a)-21(b), ¶0148) said p-type doped GaN capping layer (14) into 10multiple p-type doped GaN capping patterns (e.g., pGaN 14) (Udrea, Figs. 2, 15, 19, 21(a)-21(b), ¶0116, ¶0120, ¶0145, ¶0147), wherein said GaN layer (2/3) under parts of said p-type doped GaN capping patterns (14) is converted into gate depletion regions (e.g., portions of the 2DEG layer under the p-type GaN capping layers are depleted) (Udrea, Figs. 2, 15, 19, 21(a)-21(b), ¶0116, ¶0124), and said GaN layer not covered by said p-type doped GaN capping patterns in said resistor region (32) functions as 2DEG resistors (e.g., 2DEG beneath regions not covered with p-type doped GaN capping layers act as a resistance) (Udrea, Figs. 2, 15, 19, 21(a)-21(b), ¶0148);
forming a passivation layer (6/7, as in Fig. 2) (Udrea, Figs. 2, 21(a)-21(b), ¶0117-¶0118, ¶0147) on said GaN layer (2/3) and said p-type doped GaN capping patterns;
forming multiple sources (e.g., a plurality of sources 8 in the region 205 and 12 in the region 210 (as in Fig. 15)) (Udrea, Figs. 2, 15, 19, 21(a)-21(b), ¶0116, ¶0118, ¶0142, ¶0145) and drains (e.g., a plurality of drains 9 in the region 205 and 16 in the region 210 (as in Fig. 15)) on said GaN layer (2/3);
forming multiple gates (e.g., a plurality of gates 15/10) (Udrea, Figs. 2, 15, 19, 21(a)-21(b), ¶0116, ¶0118, ¶0142) on said p-type doped GaN capping patterns (e.g., 14/11), wherein said gates (10), said sources (8) and said drains (9) in said high-voltage device region (205) constitute high-voltage HEMTs, and said gates (15), said sources (12) and said drains (16) in said low-voltage device region (210) constitute low-voltage logic FETs.
Further, Udrea does not specifically disclose forming multiple sources and drains in said passivation layer; forming multiple gates in said passivation layer.
However, Lin teaches forming an integrated circuit comprising multiple HEMT devices (104, 108, 110) (Lin, Fig. 12B, ¶0013-¶0016, ¶0067, ¶0070, ¶0072) including multiple sources (216s) and drains (216d) in a passivation layer (1204), and forming multiple gates (214) in said passivation layer (1204), to provide improved integrated circuit comprising GaN high-voltage and high-power transistors having smaller size and improved performance characteristics (Lin, ¶0013-¶0016, ¶0072).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of manufacturing a resistor-transistor-logic circuit of Udrea by forming multiple sources and drains in the passivation layer as taught by Lin to have the method of manufacturing a resistor-transistor-logic circuit, comprising: forming multiple sources and drains in said passivation layer; forming multiple gates in said passivation layer, in order to provide improved integrated circuit comprising GaN high-voltage and high-power transistors having smaller size and improved performance characteristics (Lin, ¶0013-¶0016, ¶0072).
Regarding claim 5, Udrea in view of Lin discloses the method of manufacturing a resistor-transistor-logic circuit of claim 1. Further, Udrea discloses the method of manufacturing a resistor-transistor-logic circuit, wherein field plate structures (e.g., field plates 29 connected to the second gate 15 and extending between the second sources 12 and the second drain 16, as in Fig. 18) (Udrea, Figs. 18, 21(a)-21(b), ¶0116, ¶0117, ¶0144) are formed on said passivation layer (e.g., 30), but does not specifically disclose that field plate structures are formed simultaneously in the step of forming said gates.
However, Udrea teaches that field plate (29) is formed on the passivation layer (30) and connected to said gate (15) that is beneficial due to the majority of the potential drop occurring at the 2DEG vertically beneath this region (Udrea, Figs. 18, 21(a)-21(b), ¶0116-¶0118, ¶0144, ¶0147-¶0148).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of manufacturing a resistor-transistor-logic circuit of Udrea/Lin by forming field plate structures connected to the sources and drains as taught by Udrea to have the method of manufacturing a resistor-transistor-logic circuit, wherein field plate structures are formed simultaneously in the step of forming said gates, in order to provide improved integrated circuit comprising GaN high-voltage and high-power transistors with improved performance characteristics (Udrea, ¶0015-¶0018, ¶0147-¶0148).
Regarding claim 6, Udrea in view of Lin discloses the method of manufacturing a resistor-transistor-logic circuit of claim 1. Further, Udrea discloses the method of manufacturing a resistor-transistor-logic circuit, wherein field plate structures (e.g., field plates connected to the first source 8 and the fist drain 9 and extending over the first gate 10, as in Fig. 2) (Udrea, Figs. 2, 18, 21(a)-21(b), ¶0116, ¶0117, ¶0144, ¶0147-¶0148) are formed on said passivation layer (e.g., 7) and connected to said sources and said drains (8 and 9), but does not specifically disclose that field plate structures are formed simultaneously in the step of forming said sources and said drains.
However, Udrea teaches forming field plates connected to said sources and said drains (8 and 9) and extending over the first gate (10) of the high-voltage transistor (205), to control the electric field (Udrea, Figs. 2, 18, 21(a)-21(b), ¶0116-¶0118, ¶0144, ¶0147-¶0148).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of manufacturing a resistor-transistor-logic circuit of Udrea/Lin by forming field plate structures connected to the sources and drains as taught by Udrea to have the method of manufacturing a resistor-transistor-logic circuit, wherein field plate structures are formed simultaneously in the step of forming said sources and said drains, in order to provide improved integrated circuit comprising GaN high-voltage and high-power transistors with improved performance characteristics (Udrea, ¶0015-¶0018, ¶0147-¶0148).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0168599 to Udrea in view of Lin (US 2020/0105741) as applied to claim 1, and further in view of Hill et al. (US 2015/0179566, hereinafter Hill).
Regarding claim 2, Udrea in view of Lin discloses the method of manufacturing a resistor-transistor-logic circuit of claim 1. Further, Udrea does not specifically disclose further comprising performing a mesa etching process to said GaN layer to form a GaN mesa isolation region before forming said p-type doped GaN capping layer, and said AlGaN barrier layer is on said GaN mesa isolation region.
However, Lin teaches performing an etching process to the GaN layer (204/314) (Lin, ¶0025, ¶0067, ¶0071- ¶0072) to form a GaN isolation region as trench isolation structures (208) before forming the p-type doped GaN capping layer (214a), and the AlGaN barrier layer (316) is on the GaN region (314) surrounded by the isolation structures (208).
Further, Hill teaches forming an integrated circuit (Hill, Figs. 1-2, ¶0022-¶0024, ¶0026-¶0033, ¶0043-¶0053) comprising GaN HEMT transistor and performing mesa etching process (Hill, Figs. 1-2, ¶0051) to form isolation regions (146) to define the active area of the GaN HEMT transistor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of manufacturing a resistor-transistor-logic circuit of Udrea by forming the isolation regions as taught by Lin, wherein the isolation regions are formed by mesa etching process of Hill to have the method of manufacturing a resistor-transistor-logic circuit, further comprising performing a mesa etching process to said GaN layer to form a GaN mesa isolation region before forming said p-type doped GaN capping layer, and said AlGaN barrier layer is on said GaN mesa isolation region, in order to provide improved integrated circuit comprising GaN high-voltage and high-power transistors having smaller size and improved performance characteristics; and to provide improved integrated circuit for high frequency applications (Lin, ¶0013-¶0016, ¶0072; Hill, ¶0022-¶0025, ¶0051).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0168599 to Udrea in view of Lin (US 2020/0105741) as applied to claim 1, and further in view of Marinella et al. (US Patent No. 9,761,675, cited in IDS of 09/09/2024, hereinafter Marinella) and Wang et al. (US Patent No. 5,037,766, hereinafter Wang).
Regarding Claim 3, Udrea in view of Lin discloses the method of manufacturing a resistor-transistor-logic circuit of claim 1. Further, Udrea does not specifically disclose the method, further comprising forming a patterned undoped polysilicon layer on said passivation layer to function as an undoped polysilicon resistor.
However, Marinella teaches forming a resistive element above the HEMT device (Marinella, Figs. 1A-1C, Col. 2, lines 24-42, Col. 6, lines 26-67; Col. 7, lines 1-63; Col. 8, lines 15-67; Col. 9, lines 1-30; lines 34-54; Col. 11, lines 13-35) comprising a plurality of resistor elements formed by patterning a thin film of a resistive material (Marinella, Figs. 1A-1C, Col. 9, lines 1-6; Col. 10, lines 56-62) on a passivation layer (e.g., 380-382), wherein the resistive material including silicon material having desired resistivity, wherein the resistive elements provides improved electric field distribution in the GaN-based power semiconductor device, minimizes power dissipation in the OFF-state dissipation in the semiconductor device, enhances breakdown voltage and improves reliability of the power device.
Further, Wang teaches forming a resistor element (Wang, Figs. 1, 3a-3c, Col. 1, lines 51-67; Col. 2, lines 1-12; lines 37-67) comprised of highly resistive polysilicon including undoped intrinsic polysilicon layer (2) to provide scaled down resistor having a high resistivity.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the method of manufacturing a resistor-transistor-logic circuit of Udrea/Lin by forming a resistor element comprised of a resistive material above the HEMT device as taught by Marinella, wherein the resistive material includes highly resistive polysilicon including undoped intrinsic polysilicon as taught by Wang to have the method of manufacturing a resistor-transistor-logic circuit, further comprising forming a patterned undoped polysilicon layer on said passivation layer to function as an undoped polysilicon resistor, in order to improve electric field distribution in the GaN-based power semiconductor device, to minimize power dissipation in the OFF-state dissipation in the semiconductor device, to enhance breakdown voltage and reliability of the power device; and to provide scaled down resistor having a high resistivity (Marinella, Col. 2, lines 24-42, Col. 6, lines 50-67; Col. 8, lines 39-67; Col. 9, lines 34-54; Wang, Col. 1, lines 51-67; Col. 2, lines 1-12).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0168599 to Udrea in view of Lin (US 2020/0105741) as applied to claim 1, and further in view of Marinella (US Patent No. 9,761,675) and Elhami Khorasani et al. (US 2020/0266263, hereinafter Elhami Khorasani).
Regarding Claim 4, Udrea in view of Lin discloses the method of manufacturing a resistor-transistor-logic circuit of claim 1. Further, Udrea does not specifically disclose the method, further comprising forming a patterned doped polysilicon layer on said passivation layer to function as a doped polysilicon resistor.
However, Marinella teaches forming a resistive element above the HEMT device (Marinella, Figs. 1A-1C, Col. 2, lines 24-42, Col. 6, lines 26-67; Col. 7, lines 1-63; Col. 8, lines 15-67; Col. 9, lines 1-30; lines 34-54; Col. 11, lines 13-35) comprising a plurality of resistor elements formed by patterning a thin film of a resistive material (Marinella, Figs. 1A-1C, Col. 9, lines 1-6; Col. 10, lines 56-62) on a passivation layer (e.g., 380-382), wherein the resistive material including silicon material having desired resistivity, wherein the resistive elements provides improved electric field distribution in the GaN-based power semiconductor device, minimizes power dissipation in the OFF-state dissipation in the semiconductor device, enhances breakdown voltage and improves reliability of the power device.
Further, Elhami Khorasani teaches forming a high voltage resistor (221) (Elhami Khorasani, Fig. 2, ¶0007, ¶0021-¶0032) on the passivation layer (113) and comprised of patterned doped polysilicon (e.g., resistor portions 222 and 223) (Elhami Khorasani, Fig. 2, ¶0031-¶0032) having desired resistivity, to reduce the electric fields in the semiconductor device and not to increase the size of the semiconductor device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the method of manufacturing a resistor-transistor-logic circuit of Udrea/Lin by forming a resistor element comprised of a resistive material above the HEMT device as taught by Marinella, wherein the resistive material includes patterned doped polysilicon as taught by Elhami Khorasanto have the method of manufacturing a resistor-transistor-logic circuit, further comprising forming a patterned doped polysilicon layer on said passivation layer to function as a doped polysilicon resistor, in order to improve electric field distribution in the GaN-based power semiconductor device, to minimize power dissipation in the OFF-state dissipation in the semiconductor device, to enhance breakdown voltage and reliability of the power device; and to reduce the electric fields in the semiconductor device and not to increase the size of the semiconductor device (Marinella, Col. 2, lines 24-42, Col. 6, lines 50-67; Col. 8, lines 39-67; Col. 9, lines 34-54; Elhami Khorasani, ¶0007, ¶0031-¶0032).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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