Prosecution Insights
Last updated: October 25, 2026
Application No. 18/830,731

POWER SEMICONDUCTOR DEVICES INCLUDING DEEP SHIELDING REGIONS

Non-Final OA §102§103
Filed
Sep 11, 2024
Examiner
ZHU, SHENG-BAI
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed Inc.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
8m
Est. Remaining
68%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
449 granted / 721 resolved
-5.7% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
60 currently pending
Career history
796
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
69.0%
+29.0% vs TC avg
§102
22.9%
-17.1% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 721 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Detailed Action Restriction/Election Applicants’ election with traverse of Claims 1-21 in the reply filed on 10/2/2026 is acknowledged. The traversal is on the ground(s) that the instant application does not provide a showing of serious burden. This is not found persuasive because as agreed by the Applicant that the identified inventions are distinct and not obvious variants of each other. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). The requirement is still deemed proper and is therefore made FINAL Claim Rejections – 35 U.S.C. 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 1, 4, 5, 8, 9, 14, 18 and 19 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujiwara (U.S. Patent Pub. No. 2013/0105889). Regarding Claim 1 FIG. 1 of Fujiwara discloses a power semiconductor device, comprising: a semiconductor structure (12) comprising a first side, a second side, and a drift region (48) of a first conductivity type (n) therebetween; and implanted regions (44+46) of a second conductivity type (p) in the semiconductor structure adjacent the first side of the semiconductor structure, wherein the implanted regions comprise a first dopant material (Al) [0099] and a second dopant material (B) [0088], the second dopant material is between the first dopant material and the second side of the semiconductor structure, and an atomic weight of the second dopant material is lighter than that of the first dopant material. Regarding Claim 4 FIG. 1 of Fujiwara discloses a source contact (40) and a gate (24) on the first side of the semiconductor structure, wherein the gate is in or on a portion of the drift region between the implanted regions, wherein the implanted regions are support shielding regions of a transistor comprising the source contact and the gate. Regarding Claim 5 FIG. 1 of Fujiwara discloses a gate trench (20) including the gate (24) therein extending into the portion of the drift region from the first side of the semiconductor structure toward the second side, wherein the support shielding regions are spaced apart from opposing sidewalls of the gate trench and extend toward the second side beyond a bottom surface of the gate trench. Regarding Claim 8 FIG. 1 of Fujiwara discloses lateral spacings between the support shielding regions are non-uniform over respective depths thereof. Regarding Claim 9 FIG. 1 of Fujiwara discloses surfaces of the drift region comprising the implanted regions therein are recessed relative to at least a portion of the drift region therebetween. Regarding Claim 14 FIG. 1 of Fujiwara discloses a power semiconductor device, comprising: a semiconductor structure (12) comprising a first side, a second side, and a drift region (48) of a first conductivity type (n) therebetween; and implanted regions (46) of a second conductivity type (p) in the semiconductor structure adjacent the first side of the semiconductor structure, wherein an atomic weight of the material (B) of the second conductivity type is less than that of aluminum (Al). Regarding Claim 18 FIG. 1 of Fujiwara discloses a source contact (40) and a gate (24) on the first side of the semiconductor structure, wherein the gate is in or on a portion of the drift region between the implanted regions, wherein the implanted regions are support shielding regions of a transistor comprising the source contact and the gate. Regarding Claim 19 FIG. 1 of Fujiwara discloses a gate trench (20) including the gate (24) therein extending into the portion of the drift region from the first side of the semiconductor structure toward the second side, wherein the support shielding regions are spaced apart from opposing sidewalls of the gate trench and extend toward the second side beyond a bottom surface of the gate trench. Claims 1-4, 10, 11, 13, 14, 20 and 21 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mizukami (U.S. Patent Pub. No. 2006/0267022). Regarding Claim 1 FIG. 10 of Mizukami discloses a power semiconductor device, comprising: a semiconductor structure comprising a first side, a second side, and a drift region (4) of a first conductivity type (n) therebetween; and implanted regions (15) of a second conductivity type (p) in the semiconductor structure adjacent the first side of the semiconductor structure, wherein the implanted regions comprise a first dopant material (Al) and a second dopant material (B), the second dopant material is between the first dopant material and the second side of the semiconductor structure, and an atomic weight of the second dopant material is lighter than that of the first dopant material. Regarding Claim 2 FIG. 10 of Mizukami discloses the atomic weight of the second dopant material (B) is less than that of aluminum (Al). Regarding Claim 3 FIG. 10 of Mizukami discloses the second dopant material comprises at least one of boron (B), beryllium (Be), or magnesium (Mg). Regarding Claim 4 FIG. 18 of Mizukami discloses a source contact (18) and a gate (28) on the first side of the semiconductor structure, wherein the gate is in or on a portion of the drift region between the implanted regions, wherein the implanted regions are support shielding regions of a transistor comprising the source contact and the gate. Regarding Claim 10 FIG. 44 of Mizukami discloses an anode contact (66) on the first side of the semiconductor structure, wherein the anode contact comprises a metal that defines a Schottky barrier with the drift region, wherein the implanted regions (60) are well regions of a diode comprising the Schottky barrier. Regarding Claim 11 FIG. 19 of Mizukami discloses the drift region comprises an active region (34) and an edge termination region (8) that is between the active region and a peripheral edge of the semiconductor structure, and wherein the implanted regions are termination rings that extend into the edge termination region. Regarding Claim 13 FIG. 19 of Mizukami discloses the semiconductor structure comprises a silicon carbide substrate [0016] and/or one or more silicon carbide epitaxial layers, and the implanted regions further comprise carbon (C) [0021]. Regarding Claim 14 FIG. 10 of Mizukami discloses a power semiconductor device, comprising: a semiconductor structure comprising a first side, a second side, and a drift region (4) of a first conductivity type (n) therebetween; and implanted regions (12) of a second conductivity type (p) in the semiconductor structure adjacent the first side of the semiconductor structure, wherein an atomic weight of the material (B) of the second conductivity type is less than that of aluminum (Al). Regarding Claim 20 FIG. 44 of Mizukami discloses an anode contact (66) on the first side of the semiconductor structure, wherein the anode contact comprises a metal that defines a Schottky barrier with the drift region, wherein the implanted regions (60) are well regions of a diode comprising the Schottky barrier. Regarding Claim 21 FIG. 19 of Mizukami discloses the drift region comprises an active region (34) and an edge termination region (8) that is between the active region and a peripheral edge of the semiconductor structure, and wherein the implanted regions are termination rings that extend into the edge termination region. Claims 14-17 and 21 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okamura (U.S. Patent Pub. No. 2013/0221376). Regarding Claim 14 FIG. 1 of Okamura discloses a power semiconductor device, comprising: a semiconductor structure (1) comprising a first side, a second side, and a drift region (10) of a first conductivity type [0059] therebetween; and implanted regions (15) comprising a material (boron) of a second conductivity type in the semiconductor structure adjacent the first side of the semiconductor structure, wherein an atomic weight of the material of the second conductivity type is less than that of aluminum [0058]. Regarding Claim 15 FIG. 1 of Okamura discloses the material of the second conductivity type comprises at least one of boron (B), beryllium (Be), or magnesium (Mg) [0058]. Regarding Claim 16 FIG. 1 of Okamura discloses lateral spacings between the implanted regions are non-uniform over respective depths thereof. Regarding Claim 17 FIG. 1 of Okamura discloses the drift region comprises silicon carbide (SiC), and the implanted regions further comprise carbon (C) [0058]. Regarding Claim 21 FIG. 1 of Okamura discloses the drift region comprises an active region and an edge termination region that is between the active region and a peripheral edge of the semiconductor structure, and wherein the implanted regions (15) are termination rings that extend into the edge termination region. Claim Rejections – 35 U.S.C. 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 6, 7 and 12 rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara, in view of Konrath (U.S. Patent Pub. No. 2017/0221987). Regarding Claim 6 Fujiwara discloses Claim 5. Fujiwara is silent with respect to “a bottom shielding region of the second conductivity type under the bottom surface of the gate trench, wherein the support shielding regions extend toward the second side beyond the bottom shielding region”. FIG. 2 of Konrath discloses a similar power semiconductor device, comprising a bottom shielding region (212) of the second conductivity type under the bottom surface of the gate trench (201), wherein the support shielding regions (209) extend toward the second side beyond the bottom shielding region. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fujiwara, as taught by Konrath. The ordinary artisan would have been motivated to modify Fujiwara in the above manner for purpose of improving reliability and robustness ([0003] of Konrath). Regarding Claim 7 FIG. 2 of Konrath discloses the bottom shielding region comprises one of the first dopant material or the second dopant material [0057]. Regarding Claim 12 FIG. 2 of Konrath discloses second portions (209) of the implanted regions comprising the second dopant material laterally extend towards one another beyond first portions (212) of the implanted regions comprising the first dopant material. Claim 11 rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara, in view of Brunt (U.S. Patent Pub. No. 2017/0084700). Regarding Claim 11 Fujiwara discloses Claim 1. Fujiwara is silent with respect to “the drift region comprises an active region and an edge termination region that is between the active region and a peripheral edge of the semiconductor structure, and wherein the implanted regions are termination rings that extend into the edge termination region”. FIG. 1 of Brunt discloses a similar power semiconductor device, wherein the drift region (22) comprises an active region (32) and an edge termination region that is between the active region and a peripheral edge of the semiconductor structure, and wherein the implanted regions (14+34) are termination rings that extend into the edge termination region. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Fujiwara, as taught by Brunt. The ordinary artisan would have been motivated to modify Fujiwara in the above manner for purpose of forming buried junction structure in drift region ([0016] of Brunt). Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over Okamura, in view of Wang (CN 115458541, machine-translation provided). Regarding Claim 18 Okamura discloses Claim 14. Okamura is silent with respect to “a source contact and a gate on the first side of the semiconductor structure, wherein the gate is in or on a portion of the drift region between the implanted regions, wherein the implanted regions are support shielding regions of a transistor comprising the source contact and the gate”. FIG. 11 of Wang discloses a similar power semiconductor device, comprising a source contact (404) and a gate (103) on the first side of the semiconductor structure, wherein the gate is in or on a portion of the drift region between the implanted regions, wherein the implanted regions (406) are support shielding regions [0050] of a transistor comprising the source contact and the gate. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Okamura, as taught by Wang. The ordinary artisan would have been motivated to modify Okamura in the above manner for purpose of improving device performance in high radiation environment ([0005] of Wang). Pertinent Art U.S. Patent Pub. No. 2017/0170264. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Sep 11, 2024
Application Filed
Oct 14, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
68%
With Interview (+5.7%)
2y 10m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 721 resolved cases by this examiner. Grant probability derived from career allowance rate.

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