DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The first sentence of the abstract should be omitted.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: --MULTI-LAYER CAPACITIVE STORAGE DEVICE--
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 2 and 3 recite(s) the language (emphasis added) “the second/third conductor comprises a region where at least”, where “a region” is already recited in claim 1 and its unclear if the two limitations are different from each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishizu, US 20160351243 A1.
As to claim 1, Ishizu discloses a storage device comprising:
N memory layers (see Ishizu Fig 10 Refs 401 and 100), wherein N is an integer greater than or equal to 2 (see Ishizu Fig 10 Refs 401 and 100; Figure 10 depicts three memory layers.); a plurality of first wirings (see Ishizu Fig 4 Ref WBL1 and Fig 8 Refs 331 and 334b) extending in particular directions (see Ishizu Fig 5 Refs 201, 202, RBL, WBL1, WBL2, SL, CL1, and CL2, and Para [0131]); a plurality of second wirings extending in the particular directions (see Ishizu Fig 4 Ref SL and Fig 8 Refs 327c and 334a); a plurality of third wirings extending in the particular directions (see Ishizu Fig 4 Ref RBL and Fig 8 Refs 327d and 334d); a plurality of fourth wirings (see Ishizu Fig 4B Ref WL and Fig 7 Ref 328) extending in a second direction (see Ishizu Fig 8 Ref WL) intersecting with the first direction; and a plurality of fifth wirings (see Ishizu Fig 7 Ref 321b and Fig 8 Ref 321b) extending in the second direction, wherein
each of the N memory layers comprises a plurality of memory cells arranged in a matrix (see Ishizu Fig 10), wherein
each of the plurality of memory cells comprises a first transistor (see Ishizu Fig 4B Ref OS1-1 and Fig 7 OS1-2), a second transistor (see Ishizu Fig 4B Ref OS1-2 and Fig 7 OS1-1; The transistors are mislabeled between the relied upon figures.), and a capacitor (see Ishizu Fig 4B Ref C1 and Fig 7 Ref C1), wherein
a gate of the first transistor is electrically connected to one of the plurality of fourth wirings (see Ishizu Fig 4B Ref OS1-1 and Fig 7 OS1-2), wherein
one of a source and a drain of the first transistor is electrically connected to one of the plurality of first wirings (see Ishizu Fig 4B Ref OS1-1 and Fig 7 OS1-2) through a first conductor (see Ishizu Fig 8 Ref CNT3), wherein
one electrode of the capacitor is electrically connected to one of the plurality of fifth wirings (see Ishizu Fig 4B Ref C1 and Fig 7 Ref C1), wherein
the other electrode of the capacitor is electrically connected to the other of the source and the drain of the first transistor and a gate of the second transistor (see Ishizu Fig 4B Ref C1 and Fig 7 Ref C1), wherein
one of a source and a drain of the second transistor is electrically connected to one of the plurality of second wirings (see Ishizu Fig 4B Ref OS1-2 and Fig 7 OS1-1), wherein
the other of the source and the drain of the second transistor is electrically connected to one of the plurality of third wirings (see Ishizu Fig 4B Ref OS1-2 and Fig 7 OS1-1), and wherein
the first conductor comprises a region (see Ishizu Fig 8 Ref CNT3) where at least one of a top surface, a side surface, and a bottom surface of the first conductor is in contact with the one of the plurality of first wirings.
Ishizu does not appear to explicitly disclose a first direction that is a stacking direction of the N memory layers.
However, it would have been obvious to one skilled in the art at the time of the effective filing of the invention that periphery circuity disclosed in figure 5, reference characters 201 and 202 and figure 7 reference character 1712 requires wiring in the directions claimed in the invention, thus it is obvious that such wirings would be present in the particular directions annotated on figure 9 below.
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Ishizu does not appear to explicitly disclose the first conductor comprises a region where at least one of a top surface, a side surface, and a bottom
However, it would have been obvious to one skilled in the art at the time of the effective filing of the invention that the contact plugs, as disclosed in figure 14 connected to reference characters BL1-4. Only so many interconnect lines can be fabricated on a given metal layer, and it is obvious that contact plugs with a top surface, a side surface, and a bottom can be implemented in particular regions forming a wiring.
As to claim 2, Ishizu discloses the storage device according to claim 1, wherein
the one of the source and the drain of the second transistor is electrically connected to the one of the plurality of second wirings through a second conductor (see Ishizu Fig 7 Ref CNT1), and wherein
the second conductor comprises a region where at least one of a top surface, a side surface, and a bottom surface of the second conductor is in contact with the one of the plurality of second wirings (see Ishizu Fig 14 the contact plugs connected to BL1-4).
As to claim 3, Ishizu discloses the storage device according to claim 1, wherein
the other of the source and the drain of the second transistor is electrically connected to the one of the plurality of third wirings through a third conductor (see Ishizu Fig 7 Ref CNT5), and wherein
the third conductor comprises a region where at least one of a top surface, a side surface, and a bottom surface of the third conductor is in contact with the one of the plurality of third wirings (see Ishizu Fig 14 the contact plugs connected to BL1-4).
As to claim 4, Ishizu discloses the storage device according to claim 1, wherein
the first transistor comprises a back gate (see Ishizu Fig 4B Ref BG).
As to claim 5, Ishizu discloses the storage device according to claim 1, wherein
the first transistor comprises an oxide semiconductor (see Ishizu Paras [0076] and [0207]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 03/12/2026