Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: 0756-12872
Filling Date: 07/26/24
Priority Date: 02/04/22
Inventor: Yamazaki et al
Examiner: Bilkis Jahan
DETAILED ACTION
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Onuki et al (US 2022/0328486 A1, PCT publication date is used for the rejection).
Regarding claim 1, Onuki discloses a semiconductor device (Fig. 1) comprising: a first transistor 200a (Para. 68) and a second transistor 200b (Para. 68) over an insulating surface 214 (Para. 71), wherein the first transistor 200a and the second transistor 200b share a metal oxide 230 (Para. 65) and a first conductor 242b (Para. 71) over the metal oxide 214, wherein the first transistor 200a comprises a second conductor 242a (Para. 72) and a first insulator 250 (Para. 70, left), the second conductor 242a and the first insulator 250 being over the metal oxide, and a third conductor 260 (Para. 70, left) over the first insulator 250, wherein the second transistor 200b comprises a fourth conductor 242c (Para. 71) and a second insulator 250 (right), the fourth conductor 242c and the second insulator 250 being over the metal oxide 214, and a fifth conductor 260 (right) over the second insulator 250 (right), wherein the first insulator 250 (left) is positioned in a region between the first conductor 242b and the second conductor 242a, wherein the metal oxide 230 and the third conductor 260 overlap with each other with the first insulator 250 therebetween, wherein the second insulator 250 (right) is positioned in a region between the first conductor 242b and the fourth conductor 242c, and wherein the metal oxide 230 (right) and the fifth conductor 260 (right) overlap with each other with the second insulator 250 (right) therebetween.
4. Claim(s) 11-12 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsuzaki et al (US 2022/0172766 A1, PCT publication date is used for the rejection).
Regarding claim 11, Matsuzaki discloses a semiconductor device (Figs. 3H, 5, 11, Paras. 121, 128, 249, 248, 511, 256) comprising: a driver circuit layer 411; and N memory layers stacked 470 over the driver circuit layer 411, wherein N is an integer greater than or equal to 2, wherein the N memory layers 470 comprise a first wiring LBL, 426 extending in a first direction (Y-direction), the first direction being a stacking direction of the N memory layers 470, wherein the N memory layers 470 each comprise a plurality of memory cells 470, wherein the plurality of memory cells 470 each comprise a first transistor M2, a second transistor M3, a third transistor M4, and a capacitor C3, wherein one of a source and a drain of the first transistor M2 is electrically connected to the first wiring LBL, 426, wherein the other of the source and the drain of the first transistor M2 is electrically connected to a gate of the second transistor M3 and one electrode of the capacitor C3 (capacitor has electrodes), wherein one of a source and a drain of the second transistor M3 is electrically connected to one of a source and a drain of the third transistor M4, wherein the other of the source and the drain of the third transistor M4 is electrically connected to the first wiring LBL, 426, and wherein the first wiring LBL, 426 is a wiring provided in an opening reaching a conductor electrically connected to the driver circuit layer 411.
Regarding claim 12, Matsuzaki discloses the semiconductor device according to claim 11, wherein the first transistor M2, the second transistor, and the third transistor each comprise a metal oxide in a channel formation region (claim 16).
Regarding claim 13, Matsuzaki discloses the semiconductor device according to claim 11, wherein the driver circuit layer 411 comprises a write read circuit (Para. 85) comprising a switching circuit M10, IS (Para. 161) and a sense amplifier circuit SA (Para. 249), and wherein the switching circuit M10, IS is provided between the first wiring LBL and the sense amplifier circuit SA (Fig. 5B).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Onuki et al (US 2022/0328486 A1) in view of Yamazaki et al (WO 2015/136412 A1, copy is attached and used for the rejection).
Regarding claim 2, Onuki does not explicitly disclose the semiconductor device according to claim 1, further comprising: a third insulator over the first conductor, the second conductor, and the fourth conductor, wherein the fourth conductor comprises a portion positioned outward from an end portion of the third insulator.
However, Yamazaki discloses the semiconductor device (Fig. 8, Para. 96) according to claim 1, further comprising: a third insulator 216 (Para. 73) over the first conductor 204b, the second conductor 204a, and the fourth conductor 204a, wherein the fourth conductor 204a comprises a portion (right end) positioned outward from an end portion of the third insulator 216.
Yamazaki teaches the above modification is used to improve electrical characteristics of the device (Abstract). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Onuki structure with Yamazaki insulators as suggested above to improve electrical characteristics of the device (Abstract).
Regarding claim 3, Onuki does not explicitly disclose the semiconductor device according to claim 1, further comprising: a connection electrode, wherein the connection electrode comprises a region in contact with part of a top surface and part of a side surface of the fourth conductor.
However, Yamazaki discloses a connection electrode 142 (Fig. 8, Para. 98), wherein the connection electrode 142 comprises a region in contact with part of a top surface and part of a side surface of the fourth conductor 204a.
Yamazaki teaches the above modification is used to improve electrical characteristics of the device (Abstract). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Onuki structure with Yamazaki insulators as suggested above to improve electrical characteristics of the device (Abstract).
Regarding claim 4, Yamazaki further discloses the semiconductor device according to claim 3, wherein the connection electrode 142 comprises a region in contact with part of a bottom surface of the fourth conductor 204a.
Allowable Subject Matter
6. Claims 5-9 and 10 are allowed.
7. The following is an examiner’s statement of reasons for allowance:
8. The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed semiconductor device comprising: the first insulator is positioned over the first transistor and the second transistor, wherein the second conductor and the sixth conductor are electrically connected to each other through an opening provided in the first insulator, wherein the second insulator is positioned over the third transistor, wherein a portion where the ninth conductor, the sixth insulator, and the tenth conductor overlap with each other is positioned over the second insulator, and wherein the sixth conductor and the ninth conductor are electrically connected to each other through an opening provided in the second insulator in combination with all other limitations as recited in claim 5.
9. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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