DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 08/09/2024.
Claims 11-20 are pending in this application.
Claims 1-10 have been cancelled.
Foreign Priority
2. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 11, 13, 14, and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Frougier et al. (US 10,573,755)
Regarding claim 11, Frougier discloses a semiconductor device, comprising:
a substrate 230 (see fig. 29, fig. 30) a nanosheet channel 201, a metal gate 2730, a source/drain region 2310 and an insulating dielectric layer1910,
wherein the nanosheet channel 201 is located above the substrate 230, the metal gate 2730 surrounds the nanosheet channel 201, the source/drain region 2310 is connected to the nanosheet channel 201, and the insulating dielectric layer 1910 is located between the substrate 230 and the source/drain region 2310, and between the substrate 230 and the nanosheet channel 201.
Regarding claim 13, Frougier discloses a method of manufacturing the semiconductor device of claim 11, comprising:
forming a trench penetrating a source/drain by etching of silicon in the source/drain region (see figs. 3, 5, 7, 11, 13, 17), and filling the trench with an insulating dielectric material 1910 (fig. 19), so as to form a complete isolation between a bottom of a channel 201 and a bottom of the source/drain 2310 (fig. 29).
Regarding claim 14, Frougier discloses the manufacturing method of claim 13, comprising:
step S1: sequentially growing a sacrificial layer 205 (fig. 2) and a channel layer 201 on the substrate 230 (which comprising 230 & 225 & 220), etching the channel layer 201, the sacrificial layer 205 and a part of the substrate 230 into a plurality of periodically distributed fins, and forming a shallow trench isolation region between two adjacent fins (see figs. 5, 7);
step S2: forming a dummy gate layer 325 (and remained portion of layer 205 shown in fig. 7) on an exposed surface of the fin (fig. 7; see also col. 5, line 18-37);
step S3:
depositing a first spacer dielectric 310 (fig. 3) on both sides of the dummy gate layer 325, 330, and etching the first spacer dielectric in a horizontal direction to form a first spacer 310 (fig. 5);
performing source/drain etching on the fin to form the source/drain region on both sides of the first spacer 310 for manufacturing the source/drain (see fig. 5);
etching off an edge part of the sacrificial layer 205 in a central direction of the source/drain region to form an embedded recess 710 (fig. 7);
depositing a second spacer dielectric 910 (fig. 9), so that an entire surface is covered by the second spacer dielectric 910 and the embedded recess 710 is filled with the second spacer dielectric 910, so as to form a second spacer; and
removing a part of the second spacer dielectric 910 located in the horizontal direction by anisotropic etching (fig. 15);
step S4: performing source/drain etching on the fin through an etching process, penetrating the bottom of the channel through isotropic etching (figs. 13, 15) and depositing the insulating dielectric material 1910 (fig. 19) into the trench, so that the entire surface is covered by the insulating dielectric material 1910, so as to form the insulating dielectric layer 1910;
step S5:
performing isotropic etching on the filled insulating dielectric layer 1910, retaining a part of the insulating dielectric layer 1910 at the bottom (fig. 21);
performing isotropic etching on the second spacer 910, and removing a part of the second spacer dielectric 910 located in a vertical direction, so as to form an inner spacer 920 (fig. 15); and
step S6: epitaxially growing the source/drain region 2310 (fig. 23) on a surface of the insulating dielectric layer 1910, and doping the source/drain region (col. 9, line 64 – col. 10, line 11.
Regarding claim 16, Frougier discloses the manufacturing method of claim 14, wherein in the step S3, a material of each of the first spacer dielectric 310 and the second spacer dielectric 910 comprises one or more of: silicon nitride, doped silicon oxide and doped silicon carbide. See col. 5, lines 18-37, and lines 58-65.
Regarding claim 17, Frougier discloses the manufacturing method of claim 14, wherein in the step S4, when performing source/drain etching, a depth to width ratio h/a of the trench is greater than 1. See figs. 5, 7, 21.
Regarding claim 18, Frougier discloses the manufacturing method of claim 14, wherein in the step S4, when filling the insulating dielectric material 1910, a thickness b of a deposited thin film is greater than 0.5a. See figs. 19, 21.
6. Claims 11, 13-14, 16-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ju et al. (US 11,923,361)
Regarding claim 11, Ju discloses a semiconductor device, comprising:
a substrate 100 (see fig. 3K), a nanosheet channel 104b’-104d’, a metal gate 156A1, 156A2, a source/drain region 138 and an insulating dielectric layer 137A1, 137B1,
wherein the nanosheet channel 104b’-104d’ is located above the substrate 100, the metal gate 156A1, 156A2 surrounds the nanosheet channel, the source/drain region 138 is connected to the nanosheet channel, and the insulating dielectric layer 137A1, 137B1 is located between the substrate 100 and the source/drain region 138, and between the substrate 100 and the nanosheet channel 104b’-104d’.
Regarding claim 13, Ju discloses a method of manufacturing the semiconductor device of claim 11, comprising:
forming a trench 130 (figs. 3C, 3D) penetrating a source/drain by etching of silicon in the source/drain region, and filling the trench with an insulating dielectric material 134 (fig. 3E), so as to form a complete isolation between a bottom of a channel 104b and a bottom of the source/drain 138 (fig. 3K).
Regarding claim 14, Ju discloses the manufacturing method of claim 13, comprising:
step S1: sequentially growing a sacrificial layer 102a-102d and a channel layer 104b-104d on the substrate 100, etching the channel layer 104b-104d, the sacrificial layer 102a-102d and a part of the substrate 100 into a plurality of periodically distributed fins 101A1, 101B1, and forming a shallow trench isolation region between two adjacent fins (see fig. 3C);
step S2: forming a dummy gate layer 120A1, 120A2, 102a-102d on an exposed surface of the fin (figs. 3B-3C);
step S3:
depositing a first spacer dielectric 126’ and/or 128’ (fig. 3B) on both sides of the dummy gate layer, and etching the first spacer dielectric in a horizontal direction to form a first spacer (fig. 3C);
performing source/drain etching on the fin to form the source/drain region 130 (fig. 3C) on both sides of the first spacer for manufacturing the source/drain;
etching off an edge part of the sacrificial layer 102a-102c in a central direction of the source/drain region to form an embedded recess 132 (fig. 3D);
depositing a second spacer dielectric 134 (fig. 3E), so that an entire surface is covered by the second spacer dielectric 134 and the embedded recess 132 is filled with the second spacer dielectric 134, so as to form a second spacer; and
removing a part of the second spacer dielectric 134 located in the horizontal direction by anisotropic etching (fig. 3F);
step S4: performing source/drain etching on the fin through an etching process, penetrating the bottom of the channel 104b (fig. 3D, or fig. 4B) through isotropic etching, and depositing the insulating dielectric material 134 (fig. 3E) or 137A1 (fig. 4C) into the trench, so that the entire surface is covered by the insulating dielectric material 137A1, so as to form the insulating dielectric layer 137A-1;
step S5:
performing isotropic etching on the filled insulating dielectric layer 134, retaining a part of the insulating dielectric layer 137A1 at the bottom (figs. 3E, 3F, fig. 4C);
performing isotropic etching on the second spacer 134, and removing a part of the second spacer dielectric 134 located in a vertical direction, so as to form an inner spacer 136 (fig. 3F, fig. 4C); and
step S6: epitaxially growing the source/drain region 138 on a surface of the insulating dielectric layer 137A1 (fig. 3H), and doping the source/drain region 138 (col. 10, line 47 - col. 11, line 45).
Regarding claim 16, Ju discloses the manufacturing method of claim 14, wherein in the step S3, a material of each of the first spacer dielectric 126’ and/or 128’ and the second spacer dielectric 134 comprises one or more of: silicon nitride, doped silicon oxide and doped silicon carbide. See col. 7, lines 53-66, and col. 9, lines 39-49.
Regarding claim 17, Ju discloses the manufacturing method of claim 14, wherein in the step S4, when performing source/drain etching, a depth to width ratio h/a of the trench is greater than 1. See figs. 3C, 3D.
Regarding claim 19, Ju discloses the manufacturing method of claim 14, wherein in the step S6, when doping the source/drain region, for a P-type FET, a material of the source/drain region is boron doped SiGe, and for an N-type FET, the material of the source/drain region is phosphorus doped silicon. See col. 11, lines 6-30.
Claim Rejections - 35 U.S.C. § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al. (US 10,573,755), in view of Wu et al. (US 11,854,896).
Regarding claim 12, Frougier discloses the semiconductor device of claim 11, comprising all claimed limitation, as discussed above, and further comprising:
an interlayer dielectric layer 2510 (fig. 29), a first conductive channel 2910,
wherein the interlayer dielectric layer 2510 is located above the source/drain region 2310, the first conductive channel 2910 is provided inside the interlayer dielectric layer 2510, the first conductive channel 2910 is connected to the source/drain region.
Frougier fails to disclose:
a second conductive channel provided inside the interlayer dielectric layer, and the second conductive channel is connected to the metal gate.
Wu discloses:
A semiconductor device comprising a source/drain region 240, a metal gate 250, an interlayer dielectric layer 248 (fig. 13) and/or 256 (fig. 14), a first conductive channel 260 and a second conductive channel 270 provided inside the interlayer dielectric layer 248/256, wherein the first conductive channel 260 is connected to the source/drain region 240, and the second conductive channel 270 is connected to the metal gate 250.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Frougier to further include a second conductive channel, as that taught by Wu, in order to provide access to the metal gate, thereby to increase controls to the semiconductor device, hence to increase its performance.
Regarding claim 15, Frougier discloses the manufacturing method of claim 14, comprising all claimed limitations, as discussed above, and wherein in the step S1, a height of the fin is in a range of 10 nm to 400 nm (col. 4, line 63 – col. 5, line 17), and etching stops at the substrate or below the substrate 230. See figs. 5, 7.
Frougier does not specifically teach that wherein in the step S1, a width of the fin is in a range of 1 nm to 100 nm.
However, it has been held that where the only difference between the prior art and the claimed invention was a recitation of relative dimensions of the claimed element, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP §2144.04). It would have been obvious that a mere change in size of a component is generally recognized as being within the level of ordinary skill in the art.
It is to be expected that a change in size, thickness would be an unpatentable modification.
Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. See In re Aller, 220 F.2d 454, 105 USPQ 233,235 (CCPA 1955).
The instant specification contains no disclosure of either the critical nature of the claimed width of the fin or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).)
The claimed limitation regarding to the width of the fin does not bear any critical point that would establish patentability, and is not sufficient to patentable distinguish over the prior art, therefore being considered as unpatentable limitation(s) because it would have involve only a mere change in size/thickness of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP §2144.04).
9. Claims 12, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ju et al. (US 11,923,361), and further in view of Wu et al. (US 11,854,896).
Regarding claim 12, Ju discloses the semiconductor device of claim 11, comprising all claimed limitation, as discussed above, and further comprising:
an interlayer dielectric layer 140,
wherein the interlayer dielectric layer 140 is located above the source/drain region 138.
Ju fails to disclose:
a first conductive channel and a second conductive channel,
wherein the first conductive channel and the second conductive channel are provided inside the interlayer dielectric layer, the first conductive channel is connected to the source/drain region, and the second conductive channel is connected to the metal gate.
Wu discloses:
A semiconductor device comprising a source/drain region 240, a metal gate 250, an interlayer dielectric layer 248 (fig. 13) and/or 256 (fig. 14), a first conductive channel 260 and a second conductive channel 270 provided inside the interlayer dielectric layer 248/256, wherein the first conductive channel 260 is connected to the source/drain region 240, and the second conductive channel 270 is connected to the metal gate 250.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Ju to further include a first conductive channel and a second conductive channel, as those taught by Wu, in order to provide access to the source/drain region, and to the metal gate, thereby to increase controls to the semiconductor device, hence to increase its performance.
Regarding claim 20, Ju discloses the manufacturing method of claim 14 comprising all claimed limitations, as discussed above, and further comprising:
step S7: depositing an interlayer dielectric 140 (fig. 3H) on the source/drain region, and performing chemical mechanical polishing on the interlayer dielectric 140 until the dummy gate layer 120A1 is exposed;
step S8: etching and removing the dummy gate layer (figs. 3);
step S9: etching and removing the sacrificial layer, so as to release the channel layer to form the nanosheet channel (fig. 3J);
step S10: depositing a high K metal gate to form the metal gate 156 surrounding the nanosheet channel 104b’-104d’ (fig. 3K); and
step S11: further depositing the interlayer dielectric 140.
Ju fails to disclose:
Depositing the interlayer dielectric 140 to form contact holes in contact with the source/drain region and the metal gate respectively, etching the contact holes, and depositing a silicon compound, so as to form a first conductive channel and a second conductive channel respectively.
Wu discloses:
A semiconductor device comprising forming a source/drain region 240, a metal gate 250, depositing an interlayer dielectric layer 248 (fig. 13) and/or 256 (fig. 14) to form contact holes in contact with the source/drain region 240, etching the contact holes, and forming a first conductive channel 260 and a second conductive channel 270 in the interlayer dielectric layer 248/256, wherein the first conductive channel 260 is connected to the source/drain region 240, and the second conductive channel 270 is connected to the metal gate 250.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Ju to further include a first conductive channel and a second conductive channel, as those taught by Wu, in order to provide access to the source/drain region, and to the metal gate, thereby to increase controls to the semiconductor device, hence to increase its performance.
Wu may not particularly teach depositing a silicon compound, so as to form a first conductive channel and a second conductive channel respectively.
However, it would have been obvious to one of ordinary skills in the art at the time the invention was made that conductive materials such as metal, polysilicon, or silicon compound, are well known and common materials for making the source/drain/gate contacts, that selecting a known material on the basis of its suitability for the intended use is just within the general skill of a worker in the art.
MPEP § 2144.07 states that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol; “Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle.” 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of aknown plastic to make a container of a type made of plastics prior to the invention washeld to be obvious); Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323(Fed. Cir. 1988) (Claimed agricultural bagging machine, which differed from a prior art machine only in that the brake means were hydraulically operated rather than mechanically operated, was held to be obvious over the prior art machine in view of references which disclosed hydraulic brakes for performing the same function, albeit in a different environment.).
Caterpillar Inc. v. Deere & Co., 224 F.3d 1374, 56USPQ2d 1305 (Fed. Cir. 2000); Al-Site Corp. v. VSI Int ’ l, Inc., 174 F.3d 1308, 1316, 50 USPQ2d 1161, 1165 (Fed. Cir. 1999); Chiuminatta Concrete Concepts, Inc. v. Cardinal Indus. Inc., 145 F.3d 1303, 1309, 46 USPQ2d 1752, 1757 (Fed. Cir. 1998); Lockheed Aircraft Corp. v. United States , 193 USPQ 449, 461 (Ct. Cl. 1977 ); Data Line Corp. v. Micro Technologies, Inc., 813 F.2d 1196, 1 USPQ2d 2052 (Fed. Cir. 1987). In re Leshin, 125 USPQ 416.
See also MPEP § 2183.
Conclusion
10. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 July 30, 2026
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