Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kimura et al. [US PGPUB 20050045933] (hereinafter Kimura).
Regarding claim 1, Kimura teaches a storage device comprising:
a first transistor (T1, see annotated Fig. 25, Para 182);
a second transistor (T2, see annotated Fig. 25, Para 182);
a first capacitor (C1, see annotated Fig. 25, Para 181); and
a second capacitor (C2, see annotated Fig. 25, Para 181);
wherein the first capacitor comprises a first electrode and a second electrode (Para 181, see annotated Fig. 25),
wherein the second capacitor comprises the first electrode and a third electrode (Para 181, see annotated Fig. 25),
wherein one of a source and a drain (48, Para 185) of the first transistor is electrically connected to the second electrode (see annotated Fig. 25),
wherein one of a source and a drain (48, Para 185) of the second transistor is electrically connected to the third electrode (see annotated Fig. 25), and
wherein the first electrode comprises a portion overlapping with each of the second electrode, the third electrode, the first transistor, and the second transistor (see annotated Fig. 25) and is supplied with a fixed potential or a ground potential (Para 181).
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Annotated Fig. 25
Regarding claim 3, Kimura teaches a storage device further comprising:
a connection electrode (46, Para 184),
wherein the other of the source and the drain (shared source/drain, see annotated Fig. 25) of the first transistor is electrically connected to the connection electrode (see annotated Fig. 25), and
wherein the other of the source and the drain (shared source/drain, see annotated Fig. 25) of the second transistor is electrically connected to the connection electrode (see annotated Fig. 25).
Regarding claim 11, Kimura teaches a storage device wherein a top surface of the second electrode comprises a depressed portion, and wherein the first electrode comprises a protruding portion engaging with the top surface of the second electrode (Fig. 25).
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lajoie et al. [US PGPUB 20230290722] (hereinafter Lajoie).
Regarding claim 1, Lajoie teaches a storage device comprising:
a first transistor (152q, Fig. 1, Para 27);
a second transistor (152p, Fig. 1, Para 27);
a first capacitor (102q, Fig. 1, Para 27); and
a second capacitor (102p, Fig. 1, Para 27);
wherein the first capacitor comprises a first electrode (112p/172, Para 30) and a second electrode (104q, Para 30, Fig. 1),
wherein the second capacitor comprises the first electrode and a third electrode (104p, Para 30, Fig. 1),
wherein one of a source and a drain (region of the transistor connected to 158q, Para 45) of the first transistor is electrically connected to the second electrode (Fig. 1),
wherein one of a source and a drain (region of the transistor connected to 158p, Para 45) of the second transistor is electrically connected to the third electrode (Fig. 1), and
wherein the first electrode comprises a portion overlapping with each of the second electrode, the third electrode, the first transistor, and the second transistor (Fig. 1) and is supplied with a fixed potential or a ground potential (Para 54; where portion 172 is connected to interconnect 171 which is connected to ground terminal).
Regarding claim 2, Lajoie teaches a storage device wherein the first electrode comprises a portion located above the first transistor and a portion located on a side of the first transistor (Fig. 1; i.e., portion of 112p/172 to excludes that portion overlapping with capacitor 102p).
Regarding claim 14, Lajoie teaches a storage device wherein a top surface of the second electrode comprises a depressed portion (Fig. 1), and
wherein the first electrode comprises a protruding portion engaging with the top surface of the second electrode (Fig. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Okudaira et al. [US Patent 6078072] in view of Kimura (hereinafter Okudaira).
Regarding claim 1, Okudaira teaches a storage device comprising:
a first transistor (left transistor 20 (Col. 8, line 4) –i.e., T1, see annotated Fig. 1);
a second transistor (right transistor 20 (Col. 8, line 4) –i.e., T1, see annotated Fig. 1);
a first capacitor (left capacitor 10 (Col. 8, line 5) –i.e., C1, see annotated Fig. 1); and
a second capacitor (right capacitor 10 (Col. 8, line 5) –i.e., C2, see annotated Fig. 1),
wherein the first capacitor comprises a first electrode (9, Col. 8 lines 33-35 Fig. 1) and a second electrode (1 in capacitor C1, Col. 8 lines 33-35 Fig. 1),
wherein the second capacitor comprises the first electrode and a third electrode (1 in capacitor C2, Col. 8 lines 33-35 Fig. 1),
wherein one of a source and a drain (15, Col. 8 line 9) of the first transistor is electrically connected to the second electrode (Fig. 1),
wherein one of a source and a drain (15, Col. 8 line 9) of the second transistor is electrically connected to the third electrode (Fig. 1), and
wherein the first electrode comprises a portion overlapping with each of the second electrode, the third electrode, the first transistor, and the second transistor (Fig. 1).
Okudaira does not specifically disclose that the first electrode is supplied with a fixed potential or a ground potential.
Referring to the invention of Kimura, Kimura teaches electrical connectivity to the capacitor of a device (Fig. 25), wherein, the upper electrode 54 (common electrode) is connected to a fixed potential (Para 181).
In view of such teaching by Kimura, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Okudaira comprise the teachings of Kimura at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C); i.e., to bias the capacitor.
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Annotated Fig. 1
Regarding claim 10, Okudaira teaches a storage device wherein each of the first electrode and the second electrode has a flat-plate shape (Fig. 1).
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lajoie in view of Tan [US Patent 6137711].
Regarding claim 3, Lajoie teaches a storage device further comprising:
wherein the other of the source and the drain (region of the transistor connected to 154q, Para 45) of the first transistor is electrically connected to source contact 154q which is connected to a bit line (Para 45, Fig. 1), and
wherein the other of the source and the drain (region of the transistor connected to 154p, Para 45) of the second transistor is electrically connected to source contact 154q which is connected to a bit line (Para 45, Fig. 1).
Lajoie does not specifically disclose a connection electrode; and
wherein each of the other of the source and the drain of the first and second transistor is electrically connected to the connection electrode.
Referring to the invention of Tan, Tan discloses a structure of a memory cell with two cells connected with one another (Fig. 1), wherein respective one source and drain of the transistors in each cells are connect to respective capacitor and wherein the other source and drain of the respective transistors are connected to share a bit line 14 (Col. 3, lines 32-43).
In view of such teaching by Tan, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Lajoie comprise the teachings of Tan at least based on the rationale of applying known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
In view of the connectivity disclosed by Tan, a person having ordinary skills in the art will find it obvious to have a connection electrode electrically connected to each of the other of the source and the drain of the first and second transistor of Lajoie’s invention.
Regarding claim 12, Lajoie teaches a storage device further comprising:
wherein the other of the source and the drain (region of the transistor connected to 154q, Para 45) of the first transistor is electrically connected to source contact 154q which is connected to a bit line (Para 45, Fig. 1), and
wherein the other of the source and the drain (region of the transistor connected to 154p, Para 45) of the second transistor is electrically connected to source contact 154q which is connected to a bit line (Para 45, Fig. 1).
Lajoie does not specifically disclose a connection electrode; and
wherein each of the other of the source and the drain of the first and second transistor is electrically connected to the connection electrode.
Referring to the invention of Tan, Tan discloses a structure of a memory cell with two cells connected with one another (Fig. 1), wherein respective one source and drain of the transistors in each cells are connect to respective capacitor and wherein the other source and drain of the respective transistors are connected to share a bit line 14 (Col. 3, lines 32-43).
In view of such teaching by Tan, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Lajoie comprise the teachings of Tan at least based on the rationale of applying known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
In view of the connectivity disclosed by Tan, a person having ordinary skills in the art will find it obvious to have a connection electrode electrically connected to each of the other of the source and the drain of the first and second transistor of Lajoie’s invention.
Claims 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lajoie in view of Matsuzaki et al. [US PGPUB 20170117283] (hereinafter Matsuzaki).
Regarding claim 13, the modified invention of Lajoie teaches the limitation of claim 2 upon which it depends.
The modified invention does not specifically disclose a storage device wherein each of the first electrode and the second electrode has a flat-plate shape.
Referring to the invention of Matsuzaki, Matsuzaki discloses forming capacitors for memory cells planar capacitor can be implemented in lieu of trench capacitors (Para 422).
In view of such teaching by Matsuzaki, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention implement a planar capacitor (thus the electrode of the capacitors having flat-plate shape) as taught by Matsuzaki to reduce bulkiness or at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B).
Allowable Subject Matter
Claims 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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