Prosecution Insights
Last updated: August 14, 2026
Application No. 18/834,482

PROCESS FOR FABRICATING A DOUBLE SEMICONDUCTOR-ON-INSULATOR STRUCTURE

Non-Final OA §103§112
Filed
Jul 30, 2024
Priority
Jan 31, 2022 — FR FR2200850 +1 more
Examiner
TURNER, BRIAN
Art Unit
Tech Center
Assignee
Soitec
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
632 granted / 760 resolved
+23.2% vs TC avg
Minimal +4% lift
Without
With
+4.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
40 currently pending
Career history
817
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
61.4%
+21.4% vs TC avg
§102
22.2%
-17.8% vs TC avg
§112
12.8%
-27.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 760 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "an oxide layer" in lines 8 and 16. There is insufficient antecedent basis for these limitations in the claim. Line 6 recites “a first step of formation of an oxide layer”, such that the subsequent recitations of “an oxide layer” in lines 8 and 16 lack proper antecedent basis. It appears the method as supported by the as-filed written description includes a formation of oxide material on front and back surfaces of a handle substrate, which results in a first electrically insulating layer on a front side of the handle wafer, and an oxide layer on a back side of the handle substrate. In a second step, additional oxide material is formed on front and back surfaces of a handle substrate, which forms a second electrically insulating layer on the front side of the handle wafer, and increases the oxide layer thickness on the back side of the handle substrate. For the purpose of compact prosecution, the Examiner has interpreted claim 1 to mean: “…a first step of formation of an oxide material on a front side and a back side of the handle substrate, to form the first electrically insulating layer on the front side of the handle substrate and an oxide layer on the back side of the handle substrate” and “…a second step of formation of [[an]] a second oxide material on the front side of the first semiconductor-on-insulator substrate…” In addition, to maintain proper antecedent basis, claim 13 has been interpreted to mean: 13. “…further comprising treating a surface of the first single semiconductor-on-insulator substrate, before the second step of formation of [[an]] the second oxide material on the surface of the first semiconductor-on-insulator substrate…” Claims 2-15 depend on claim 1, and are rejected under 35 USC § 112(b) for implicitly including the allowable subject matter above. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Schwarzenbach et al. (PG Pub. No. US 2021/0202326 A1) in view of Linn et al. (Patent No. US 5,849,627 A). Regarding claim 16, Schwarzenbach teaches a double semiconductor-on-insulator structure (fig. 3F), comprising, in succession from a back side to a front side of the structure: a handle substrate (¶ 0100: 1); a first electrically insulating layer (¶ 0100: 2a) having a thickness of at least 100 nm (¶ 0079); a first single-crystal semiconductor layer (¶ 0101: 2b) having a thickness of at least 50 nm (¶ 0114); a second electrically insulating layer (¶ 0102: 3a) having a thickness of at least 100 nm (¶ 0079); and a second single-crystal semiconductor layer (¶ 0103: 3b) having a thickness of at least 50 nm (¶ 0114). Schwarzenbach does not teach the double semiconductor-on-insulator structure further comprises an oxide layer, the thickness of the first electrically insulating layer (2a) being less than the thickness of the oxide layer. Lin teaches a semiconductor-on-insulator structure (fig. 3D among others), comprising, in succession from a back side to a front side of the structure: an oxide (col. 4 line 7: 314) having a thickness (fig. 3D); a handle substrate (col. 4 lines 3: 312, similar to 1 of Schwarzenbach); and a first electrically insulating layer (col. 4 line 7: 316 and/or 315, similar to 2a of Schwarzenbach) having a thickness of at least 100 nm (col. 5 line 3: 4.5 um), the thickness of the first electrically insulating layer being less than the thickness of the oxide layer (col. 4 lines 7-9: thickness of 316 less than total thickness of 314). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the double semiconductor-on-insulator structure of Schwarzenbach with the oxide of Linn, as a means to provide stress compensation and restrain warpage (Linn, col. 4 lines 9-10). Regarding claim 17, Schwarzenbach in view of Linn teaches the double semiconductor-on-insulator structure of claim 16, wherein the thickness of the first single-crystal semiconductor layer is less than 500 nm (Schwarzenbach, ¶¶ 0018, 0114). Regarding claim 18, Schwarzenbach in view of Linn teaches the double semiconductor-on-insulator structure of claim 16, wherein the thickness of the second electrically insulating layer is less than 1100 nm (Schwarzenbach, ¶ 0114). Regarding claim 19, Schwarzenbach in view of Linn teaches the double semiconductor-on-insulator structure of claim 16, wherein the thickness of the second single-crystal semiconductor layer is less than 500 nm (Schwarzenbach, ¶¶ 0018, 0114). Regarding claim 20, Schwarzenbach in view of Linn teaches the double semiconductor-on-insulator structure of claim 16, wherein each of the first electrically insulating layer and the second electrically insulating layer comprises an oxide layer, respectively (Schwarzenbach, ¶¶ 0100, 0102). Allowable Subject Matter Claims 1-15 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating: “…a first step of formation of an oxide material on a front side and a back side of the handle substrate, to form the first electrically insulating layer on the front side of the handle substrate and an oxide layer on the back side of the handle substrate” and “…a second step of formation of [[an]] a second oxide material on the front side of the first semiconductor-on-insulator substrate…” as required by claim 1. Schwarzenbach teaches forming first and second electrically insulating layers on the front side of a handle substrate, but fails to teach forming an oxide layer on a back side of the handle substrate while forming the first electrically insulating layer, or increasing a thickness of the oxide layer while forming the second electrically insulating layer. Linn teaches forming an oxide layer (314) on a back side of a handle substrate (312) while forming a first electrically insulating layer (316) on a front side of the handle substrate (fig. 3a), and increasing a thickness of the oxide layer while forming a second electrically insulating layer (326) on the front side of a handle substrate (col. 4 lines 63-67 & fig. 3d: forming 326 on front of 312 increases thickness of 314 on back of 312). However, Linn fails to teach forming first and second single-crystal semiconductor layers, as required by claim 1. Claims 2-15 depend on claim 1 and are allowable for implicitly including the allowable subject matter above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRIAN TURNER/Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Jul 30, 2024
Application Filed
Jul 30, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
88%
With Interview (+4.5%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 760 resolved cases by this examiner. Grant probability derived from career allowance rate.

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