DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/22/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 06/22/2026 have been considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5 and 11 are rejected under 35 U.S.C. §103 as being unpatentable over Bandic et al., US 2017/0046221 A1 (“Bandic”), in view of Gifford et al., US 2014/0281810 A1 (“Gifford”), and further in view of WO 2020/152522 A1 (“the ’522 publication”).
Claim 1: Bandic teaches a memory device comprising:
a check bit generation portion generating a check bit from an information bit (e.g., Bandic teaches a controller configured to determine parity data corresponding to user data. Bandic, in ¶0037, teaches determining parity associated with a block of user data, including determining XOR parity data. Bandic, in ¶0068, similarly teaches receiving a block of user data and determining XOR parity data for that block. Accordingly, Bandic’s user data corresponds to the claimed information bit, and Bandic’s generated parity/ECC information corresponds to the claimed check bit);
a first memory portion storing the information bit (e.g., Bandic teaches storing user data in a primary memory device. Bandic, in ¶0021, expressly teaches determining parity data associated with a block of user data and storing the block of user data in a primary memory device);
a second memory portion storing the check bit (e.g., Bandic teaches storing at least a portion of the generated parity data in a parity memory device separate from the primary memory device. See ¶¶0021–0023 and 0039. Bandic, in ¶0066, further teaches mapping user data to memory devices 16 and corresponding parity data to parity memory devices 20);
an error detection portion performing arithmetic processing using the information bit stored in the first memory portion and the check bit stored in the second memory portion (e.g., Bandic teaches retrieving both stored user data and stored parity data and using the parity data to verify the stored user data. Bandic, in ¶0037, expressly describes XOR-based parity generation followed by use of the stored parity information for verification of the corresponding user data.
Bandic further identifies the parity information as ECC parity data for protecting stored information against corruption. See ¶¶0019 and 0038–0039.Thus, Bandic teaches the claimed error-detection/arithmetic-processing functionality).
Not explicitly taught by Bandic is:
an error correction portion correcting the information bit or the check bit in accordance with a result of the arithmetic processing, wherein the first memory portion comprises a first transistor, wherein the second memory portion comprises a second transistor in a first layer, a third transistor in a second layer, and a driver circuit comprising a fourth transistor in a third layer, wherein the first layer is over the second layer, wherein the second layer is over the third layer, wherein the first layer, the second layer and the third layer overlap each other, wherein the driver circuit is configured to drive the second transistor and the third transistor, wherein each of the first transistor and the fourth transistor comprises silicon in a channel formation region, wherein each of the second transistor and the third transistor comprises a metal oxide in a channel formation region, wherein the metal oxide comprises indium, and wherein a semiconductor layer of the second transistor and a semiconductor layer of the first transistor have different compositions.
However, Gifford teaches reading an EDAC word including stored data and corresponding check bits from memory array 850, supplying the EDAC word to EDAC decoder 860, and correcting a correctable bit error. Gifford further teaches that corrected read data may be written back to memory and that corrected/merged data are supplied to EDAC encoder 882, which recalculates the EDAC check bits. The newly generated check bits are thereafter written back into memory using check-bit write circuitry. See Gifford, discussion of Figs. 22–25, particularly the EDAC decoder 860, corrected read data register 886, EDAC encoder 882, and write drivers 884/885. Thus, Gifford expressly describes the relevant path as a read/correct/write-back path.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Gifford’s known EDAC correction circuitry into Bandic’s ECC-protected storage system. Bandic expressly identifies its parity as ECC parity and uses the parity together with stored user data to detect or verify memory errors. Gifford teaches the conventional completion of that same ECC operation: once the stored data/check information indicates a correctable error, the decoder corrects the erroneous bit and the corrected information may be restored in memory. The modification therefore amounts to employing a known error-correction technique for its established purpose in Bandic’s expressly disclosed ECC system and would predictably permit detected correctable errors to be corrected rather than merely detected.
As per the limitation: “wherein the first memory portion comprises a first transistor”, The ’522 publication expressly teaches semiconductor memory devices comprising memory cells having transistors. In particular, the ’522 publication discloses a first element layer including a first memory cell and a second element layer including a second memory cell, wherein the first and second memory cells respectively include first and second transistors. See the ’522 publication, ¶¶0010–0019, 0023–0026; claims 1, 2, 6, 9, and 10.
As per the limitation: “wherein the second memory portion comprises a second transistor in a first layer, a third transistor in a second layer, and a driver circuit comprising a fourth transistor in a third layer”; The ’522 publication teaches a vertically integrated semiconductor memory architecture including:
a first element layer comprising a first memory cell and transistor;
a second element layer comprising a second memory cell and transistor;
the second element layer vertically above the first element layer; and
a silicon substrate/device region comprising a driver circuit having a fourth transistor.
See the ’522 publication ¶¶0010–0019 and 0023–0026; claims 1, 6, 9, and 10. The reference specifically states that the first memory cell includes a first transistor, the second memory cell includes a second transistor, and the silicon substrate includes a driver circuit comprising a fourth transistor. For correspondence with the terminology of claim 1, the upper memory element layer of the ’522 publication corresponds to the claimed first layer, the lower memory element layer corresponds to the claimed second layer, and the lower silicon driver/device layer corresponds to the claimed third layer.
As per the limitation “wherein the first layer is over the second layer”; and “wherein the second layer is over the third layer”, The ’522 publication expressly teaches the vertical relationship. Its second memory-cell element layer is over its first memory-cell element layer, and those memory-cell layers are over the silicon substrate containing the driver circuitry. See ¶¶0010, 0023; claims 1 and 6.
As per the limitation: “wherein the first layer, the second layer and the third layer overlap each other”, The ’522 publication is directed to a stacked memory architecture in which the memory-cell element layers are vertically integrated over the driver-circuit substrate. Its vertically extending wiring electrically couples transistors of the stacked memory layers to underlying circuitry. See ¶¶0010–0019, 0023–0026 and the vertically stacked arrangements of Figs. 1A–1C and related embodiments. The stacked layers therefore overlap in plain view/vertical projection.
As per the limitation: “wherein the driver circuit is configured to drive the second transistor and the third transistor”, The ’522 publication teaches that corresponding source/drain portions of transistors in the different stacked memory layers are electrically connected to vertically extending wiring for connection to lower control/driver circuitry. The abstract and claims expressly describe both memory-cell transistors as electrically connected by wiring extending toward the driver/control circuitry. Thus, the same underlying peripheral/driver architecture is provided for operating the transistors in the vertically stacked memory-cell layers.
As per the limitation: “wherein each of the first transistor and the fourth transistor comprises silicon in a channel formation region”, The ’522 publication, however, teaches conventional Si transistors in the silicon substrate/driver circuitry and recognizes the integration of oxide-semiconductor memory transistors over conventional silicon-transistor circuitry. Its Background expressly explains that an OS transistor can be stacked over a Si transistor and that memory-cell array layers including OS transistors may be stacked over a substrate on which Si transistors are provided.
As per the limitation: “wherein each of the second transistor and the third transistor comprises a metal oxide in a channel formation region”, The ’522 publication expressly teaches that semiconductor layers of the transistors in its first and second stacked memory-cell layers may each comprise a metal oxide in the channel formation region. See ¶¶0011, 0019, 0025–0026; claims 2 and 9.
As per the limitation: “wherein the metal oxide comprises indium”, The ’522 publication expressly teaches that the oxide semiconductor preferably comprises In, Ga, and Zn, i.e., an In—Ga—Zn oxide/IGZO semiconductor. See ¶¶0019, 0026 and claim 10.
As per the limitation: “wherein a semiconductor layer of the second transistor and a semiconductor layer of the first transistor have different compositions”, The ’522 publication itself distinguishes conventional silicon transistors from oxide-semiconductor transistors and teaches vertical integration of the two technologies. The ’522 publication teaches a known way to obtain high-density heterogeneous memory integration by vertically stacking oxide-semiconductor memory-cell layers over silicon transistor circuitry. The reference further explains that oxide-semiconductor transistors exhibit extremely low off-state current and can be integrated over conventional silicon circuitry.
Therefore, a person of ordinary skill implementing Bandic’s separate information and parity memories would therefore have had reason to employ the ’522 publication’s known vertically integrated memory architecture to increase memory density while retaining conventional silicon peripheral/driver circuitry and using low-leakage oxide-semiconductor memory transistors. The elements would continue performing their known functions and the result—a vertically integrated heterogeneous ECC memory having separately stored user and check information—would have been predictable.
Claims 3 and 11 recites an operation method/computer readable medium of a memory device having substantially the same physical memory architecture recited in claim 1. Accordingly, claim 3 is rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding device claim.
Claim 4: Bandic, Gifford and the ’552 publication teach the operation method of the memory device according to claim 3, but fail to teach configuration bits of the information bit are not stored in successive physical addresses. However, Bandic teaches that the physical placement of logically associated data is controlled using an advanced logical-to-physical address mapping scheme. Bandic, in ¶ 0059, teaches that a logical page address may be mapped to multiple physical page addresses, and ¶¶ 0060–0061 describe storing portions of logically associated data at separately determined physical pages. Bandic also teaches that physical storage need not preserve the logical organization of the data. Address translation module 22 translates logical addresses used by the host into physical addresses actually used to store the data. See ¶¶ 0041–0043. Thus, Bandic teaches that physically stored portions of a logical data unit need not occupy a physical-address sequence corresponding to the logical ordering of that data. Although Bandic does not use the exact expression “not stored in successive physical addresses,” its logical-to-physical mapping permits logically associated information to be placed at independently selected physical locations rather than requiring consecutive physical storage. It would have been obvious to one of ordinary skill implementing Bandic’s mapping system to place constituent information data at non-successive physical locations because Bandic expressly decouples logical organization from physical placement and permits a single logical page to span multiple separately mapped physical locations. Such placement is a predictable use of Bandic’s disclosed address-translation scheme to accommodate available physical pages and storage-management requirements.
Claim 5: Bandic, Gifford and the ’552 publication teach the operation method of the memory device according to claim 3, but fail to teach configuration bits of the check bit are not stored in successive physical addresses. However, Bandic, in ¶ 0020, teaches that a controller employing an advanced logical-to-physical address mapping scheme may allocate multiple physical page addresses to store parity data. Bandic, in ¶ 0039, further teaches storing portions of parity data on physical pages separate from the page containing corresponding user data and expressly describes writing and reading different physical pages. Bandic, in ¶¶ 0065–0066, also teaches that parity information associated with a single logical page may be distributed between ordinary memory pages and a separately addressable parity memory device. Thus, Bandic teaches that constituent portions of a logical parity/check value need not be physically stored as one contiguous sequence but may be mapped among separately selected physical storage locations. Therefore, it would have been obvious to use non-successive physical locations for such parity/check bits because Bandic expressly permits parity storage to be distributed among multiple physical pages and/or separate parity memory devices in order to accommodate parity size independently of primary-memory page size and permit flexible ECC strength.
Claims 7–9 and 12 are rejected under 35 U.S.C. § 103 as being unpatentable over Bandic et al., US 2017/0046221 A1 (“Bandic”), in view of Gifford et al., US 2014/0281810 A1 (“Gifford”), and further in view of WO 2018/004663 A1 (“the ’663 publication”).
Claim 7: Bandic teaches an operation method of a memory device comprising the steps of:
generating a check bit using an information bit (e.g., Bandic teaches determining parity data corresponding to user data. In particular, Bandic teaches that controller 8 may determine parity associated with a block of user data, including determining an exclusive-OR (XOR) of the user data. See Bandic ¶ 0037. Bandic ¶ 0068 likewise teaches receiving a block of user data and determining XOR parity data for that block );
storing the information bit in a first memory portion (e.g., Bandic teaches storing user data in memory devices 16 of the primary storage array. For example, Bandic ¶ 0021 teaches determining parity data associated with a block of user data and storing the block of user data in a primary memory device);
storing the check bit in a second memory portion (e.g., Bandic teaches storing at least part of the parity data in a parity memory device separate from the primary memory device. See Bandic ¶¶ 0021–0023 and 0039. Bandic ¶ 0066 more specifically teaches mapping user data 40A and first parity data 42A1 to a physical page of memory devices 16 while mapping second parity data 42A2 to parity memory devices 20);
performing arithmetic processing using the information bit stored in the first memory portion and the check bit stored in the second memory portion (e.g., Bandic teaches reading both the stored user data and its associated stored parity data and using the parity information to verify the stored user data. Bandic ¶ 0037 expressly describes XOR-based parity generation followed by use of the stored parity to verify the stored user data. Bandic further identifies the parity as ECC parity data used to protect against corruption and explains that user and parity data may be retrieved together for decoding. See Bandic ¶¶ 0019, 0038–0039).
Not explicitly taught by Bandic is:
correcting the information bit or the check bit in accordance with a result of the arithmetic processing;
in a case where the information bit is corrected, storing the information bit subjected to the correction in the first memory portion; and
in a case where the check bit is corrected, storing the check bit subjected to the correction in the second memory portion, wherein the first memory portion comprises a transistor comprising silicon in a channel formation region, wherein the second memory portion comprises a transistor comprising a metal oxide in a channel formation region and wherein the metal oxide comprises indium.
However, Gifford teaches a memory EDAC/scrub operation in which an EDAC-protected memory word comprising stored data and check bits is read from memory array 850, decoded by EDAC decoder 860, and corrected when a correctable error is detected. See Gifford, discussion of Fig. 22. Gifford further teaches that the corrected read data are conveyed to corrected read data register 886 and, where EDAC decoder 860 has corrected a data bit, the corrected bit may be written back to memory array 850 either individually or as part of the corrected data word. See Gifford, discussion of Fig. 23. Gifford additionally teaches supplying the corrected/merged data to EDAC encoder 882 to generate new EDAC check bits and writing the new check bits into memory array 850 using check-bit write drivers 885. Id. Gifford expressly characterizes the Fig. 25 scrub path as a “read/correct/write back” path including EDAC decoder 860, corrected read data register 886, EDAC encoder 882, and write drivers 884/885. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate Gifford’s known ECC correction-and-write-back operation into Bandic’s ECC-protected storage architecture. Bandic expressly characterizes its stored parity as ECC parity and explains that the parity is used to protect user-data integrity and permit decoding/recovery of the stored information. And Gifford teaches the conventional completion of that ECC function - detecting/correcting an erroneous stored bit and rewriting the corrected information so that the stored copy again represents valid information. A person of ordinary skill implementing Bandic’s disclosed ECC system would therefore have had reason to employ Gifford’s correction-and-write-back technique to prevent a detected correctable error from remaining resident in the memory. Each component would continue to perform its known function, and the result—an ECC-protected memory in which detected correctable errors are repaired in storage—would have been predictable. Accordingly, Gifford teaches the claimed operations of correcting data/check information based on error-detection processing and storing the corrected information back into memory.
As per the limitations that “wherein the first memory portion comprises a transistor comprising silicon in a channel formation region; wherein the second memory portion comprises a transistor comprising a metal oxide in a channel formation region; and
wherein the metal oxide comprises indium”, The ’663 publication teaches a memory cell having a sensing transistor formed in silicon logic circuitry and a charging/write transistor having an amorphous oxide semiconductor channel. See the ’663 publication, Detailed Description, pp. 2–5; Figs. 1 and 3; claims 1–4 and 15–18. The ’663 publication teaches that the oxide-semiconductor charging transistor may use IGZO (indium gallium zinc oxide) and further lists IZO, In₂O₃, and ITO as suitable oxide-channel materials. Thus, the reference expressly teaches a metal-oxide channel comprising indium. The ’663 publication also explains known functional advantages of the respective transistor technologies. The oxide-semiconductor transistor is selected for very low off-state leakage and improved charge retention, while the silicon sensing transistor provides the conventional silicon logic/sensing functionality. Therefore, it would have been obvious to one of ordinary skill to implement Bandic’s expressly contemplated heterogeneous primary/parity memory arrangement using known silicon-channel and indium-containing oxide-channel memory transistor technologies such as those taught by the ’663 publication. Bandic itself provides the reason to consider different memory technologies for the respective storage portions. The ’663 publication teaches that silicon-channel and oxide-channel memory transistor technologies were known, operable together in a memory environment, and possessed different known operating characteristics. Thus, the proposed modification does not depend merely on the fact that the references can physically be combined. Rather, Bandic expressly invites use of differing memory technologies, and the ’663 publication supplies known memory-transistor technologies having differing known characteristics suitable for implementing such heterogeneous storage. The modification would have required no change to Bandic’s ECC operation: the first memory portion would continue storing information data and the second memory portion would continue storing parity/check information. The change is limited to the known transistor technology used to implement the respective storage portions, and each technology would perform its conventional memory-storage function. Accordingly, the combination would have produced the predictable result of Bandic’s ECC architecture implemented using heterogeneous silicon-channel and indium-containing oxide-channel memory technology.
As per claim 12, the limitations claimed are rejected similarly to claim 7 above.
Claim 8: Bandic, Gifford and the ’663 publication teach the operation method of a memory device according to claim 7, but fail to teach configuration bits of the information bit are not stored in successive physical addresses. However, Bandic teaches that the physical placement of logically associated data is controlled using an advanced logical-to-physical address mapping scheme. Bandic, in ¶ 0059, teaches that a logical page address may be mapped to multiple physical page addresses, and ¶¶ 0060–0061 describe storing portions of logically associated data at separately determined physical pages. Bandic also teaches that physical storage need not preserve the logical organization of the data. Address translation module 22 translates logical addresses used by the host into physical addresses actually used to store the data. See ¶¶ 0041–0043. Thus, Bandic teaches that physically stored portions of a logical data unit need not occupy a physical-address sequence corresponding to the logical ordering of that data. Although Bandic does not use the exact expression “not stored in successive physical addresses,” its logical-to-physical mapping permits logically associated information to be placed at independently selected physical locations rather than requiring consecutive physical storage. It would have been obvious to one of ordinary skill implementing Bandic’s mapping system to place constituent information data at non-successive physical locations because Bandic expressly decouples logical organization from physical placement and permits a single logical page to span multiple separately mapped physical locations. Such placement is a predictable use of Bandic’s disclosed address-translation scheme to accommodate available physical pages and storage-management requirements.
Claim 9: Bandic, Gifford and the ’663 publication teach the operation method of a memory device according to claim 7, but fail to teach configuration bits of the check bit are not stored in successive physical addresses. However, Bandic, in ¶ 0020, teaches that a controller employing an advanced logical-to-physical address mapping scheme may allocate multiple physical page addresses to store parity data. Bandic, in ¶ 0039, further teaches storing portions of parity data on physical pages separate from the page containing corresponding user data and expressly describes writing and reading different physical pages. Bandic, in ¶¶ 0065–0066, also teaches that parity information associated with a single logical page may be distributed between ordinary memory pages and a separately addressable parity memory device. Thus, Bandic teaches that constituent portions of a logical parity/check value need not be physically stored as one contiguous sequence but may be mapped among separately selected physical storage locations. Therefore, it would have been obvious to use non-successive physical locations for such parity/check bits because Bandic expressly permits parity storage to be distributed among multiple physical pages and/or separate parity memory devices in order to accommodate parity size independently of primary-memory page size and permit flexible ECC strength.
13 is rejected under 35 U.S.C. §103 as being unpatentable over Bandic et al., US 2017/0046221 A1 (“Bandic”), in view of Gifford et al., US 2014/0281810 A1 (“Gifford”), further in view of WO 2020/152522 A1 (“the ’522 publication”) and further in view of WO 2018/004663 A1 (“the ’663 publication”).
As per claim 13, the claim recites:
A memory device comprising:
a first plurality of memory cells configured to store an information bit”; “a second plurality of memory cells configured to store a check bit (e.g., Bandic teaches a primary storage array comprising a plurality of memory devices for storing user/information data and one or more separate parity memory devices for storing corresponding parity/check information. See ¶¶0021–0023 and claims 1 and 5);
a check bit generation circuit configured to generate the check bit from the information bit (e.g., Bandic teaches controller circuitry that determines XOR parity data from the user information. See ¶¶0037, 0068);
an error detection circuit configured to perform arithmetic processing using the information bit and the check bit (e.g., Bandic teaches retrieving stored user data and its associated parity and using the parity to verify the stored data. See ¶0037).
As per the limitation: an error correction circuit configured to correct the information bit in accordance with a result of the arithmetic processing, Bandic does not expressly teach the complete correction circuit.
However, Gifford supplies this limitation by teaching EDAC decoder 860, which decodes the stored data/check-bit word, corrects a correctable error, and makes corrected data available for restoration to memory. See Gifford, Figs. 22–25 and corresponding description.
For the reasons already discussed, incorporating Gifford’s known error-correction circuitry into Bandic’s expressly ECC-protected memory would have been an application of a known ECC technique for its established purpose and would have yielded predictable results.
As per the limitations: “wherein each of the first plurality of memory cells comprises a first transistor and a first capacitor”; “wherein each of the second plurality of memory cells comprises a second transistor and a second capacitor”, The ’522 publication expressly teaches this structure. Its first stacked element layer contains first memory cells, each comprising a first transistor and first capacitor, and its second stacked element layer contains second memory cells, each comprising a second transistor and second capacitor. See the ’522 publication ¶¶0010–0019, 0023–0026; claims 1 and 6. Thus, the ’522 publication directly teaches the claimed transistor-plus-capacitor memory-cell structures.
As per the limitations: “wherein the first transistor in each of the first plurality of memory cells comprises silicon”; and “wherein the second transistor in each of the second plurality of memory cells comprises In and O in a channel formation region”, the ’522 publication teaches oxide-semiconductor memory-cell transistors in vertically stacked memory layers and expressly teaches that the oxide semiconductor can comprise In, Ga, and Zn. See ¶¶0011, 0019, 0025–0026; claims 2, 9 and 10. Thus, the ’522 publication directly teaches the claimed In and O-containing channel for the second plurality.
The ’522 publication also teaches conventional silicon transistor circuitry integrated with oxide-semiconductor memory circuitry, but its preferred stacked-memory embodiments use oxide-semiconductor transistors in both memory-cell layers. Accordingly, it does not, standing alone, most directly teach assigning a silicon-channel transistor specifically to the first population of 1T1C memory cells while retaining the indium-oxide transistor in the second population.
However, The ’663 publication provides additional evidence that silicon transistors and indium-containing oxide-semiconductor transistors were known alternative/complementary transistor technologies for memory-cell circuitry.
The ’663 publication teaches a memory cell having:
a silicon sensing transistor;
an oxide-semiconductor charging transistor; and
oxide channel compositions including IGZO, IZO, and indium oxide.
See the ’663 publication, Detailed Description pp. 2–5; claims 1–4 and 15–18.
The reference explains that the oxide-semiconductor transistor provides very low off-state leakage/charge retention while the silicon transistor provides high-mobility sensing circuitry.
Bandic expressly teaches that the memory storing user/information data and the memory storing parity/check information may be different types of memory devices. See ¶¶0022–0023.
The ’522 publication teaches 1T1C-type memory cells arranged in vertically integrated populations and demonstrates the use of indium-containing oxide-semiconductor transistors in those memory cells. The ’663 publication further demonstrates that silicon-channel and indium-containing oxide-channel transistors were known memory-circuit transistor technologies that could be integrated together.
Therefore, before the effective filing date of the claimed invention, a person of ordinary skill implementing Bandic’s expressly heterogeneous primary/parity memory arrangement therefore would have had reason to implement one memory population with conventional silicon transistor memory cells and another population with the known indium-containing oxide-transistor memory cells according to the differing known device characteristics. This would not require changing the function of either Bandic memory portion: the first population would continue storing information data, and the second population would continue storing parity/check data. Rather, the modification would concern the known semiconductor technology used to implement each separately addressable memory population. Because the references already establish both heterogeneous memories and compatible silicon/oxide semiconductor memory technology, the resulting heterogeneous memory architecture would have been a predictable implementation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 8/18/2026
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