DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-12 have been considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-5, 7-9, 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bandic et al (US2017/0046221) (hereinafter D1) and further in view of Dewey et al. (US 2022/0052200 A1). (hereinafter D2).
Claim 1: D1 teaches a memory device comprising:
a check bit generation portion (item 8, fig. 1) generating a check bit from an information bit (as per [0003], the controller generate write parity data, and as per [0019], [0024]. [0044]- the controller store user data and parity data associated with the user data & [0068]);
a first memory portion (item 10, or 16, fig. 1) storing the information bit ([0028]-[0029], [0041]);
a second memory portion (item 20, fig. 1) storing the check bit ([0036], [0064 -0066]);
an error detection portion performing arithmetic processing using the information bit stored in the first memory portion and the check bit stored in the second memory portion (e.g. the controller reads the parity data and the user data to retrieve the user data – [0020]-[0021] & [0037], [003); and
an error correction portion correcting the information bit or the check bit in accordance with a result of the arithmetic processing ([0037], [0039], [0053]- the controller reads the parity data and the user data in order to decode and retrieve the user data), wherein the first memory portion comprises a first transistor ([0029]), wherein the second memory portion comprises a second transistor ([0029], [0036]).
D1 further teaches that:
the wherein the first transistor comprises silicon in a channel formation region;
wherein the second transistor comprises a metal oxide in a channel formation region; and
wherein a semiconductor layer of the second transistor and a semiconductor layer of the first transistor have different compositions.
However, D2 teaches:
Group IV materials (including silicon) for transistor channels, particularly in front-end CMOS FETs (e.g. [Background; ¶0073; claim 11]);
Metal oxide semiconductors (IGZO, ZnO, SnO, InO, etc.) as channel material for thin-film transistors (e.g. [¶0028-0030; ¶0032; claim 1]);
Integration of transistors with different semiconductor compositions in a single device, including FEOL silicon devices and BEOL oxide semiconductor devices (e.g. [¶0075; claim 11]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention, seeking to implement D1's memory architecture with separate storage for information bits and check bits, would have been motivated to select appropriate transistor technologies for each memory portion. D2 provides the express teaching that different transistor types, such as silicon-channel and metal-oxide-channel, can be advantageously integrated in a single device to achieve different performance characteristics (e.g., [¶0075; FIG. 15]). The PHOSITA would recognize that the primary storage array (storing large amounts of user data) could be implemented with mature, dense silicon-based memory technology, while the parity memory device (storing smaller amounts of critical check bits) could be implemented with metal-oxide transistors offering different characteristics.
As per claim 3, the claims recites a method of operating a memory device comprising the steps of generating a check bit (parity data), writing an information bit and the check bit to separate first and second memory portions, performing arithmetic processing (error detection) on them, correcting errors based on the result, and storing the corrected bits.As established in the rejection of claims 1 and 2, the memory device itself, comprising a primary silicon-based memory array (first memory portion) and a separate oxide semiconductor-based parity memory device (second memory portion), would have been obvious over D1 in view of D2. Furthermore, D1 teaches the core method steps performed by the controller (8): generating parity data for a block of user data ([0068]), writing the user data to the primary array, and writing the parity data to the separate parity memory device (Abstract; [0071]). The reference also teaches reading both the data and parity to "verify" the block of user data ([0037]), which inherently requires the "arithmetic processing" of error detection. Andthe remaining steps of "correcting an error" and storing the corrected bits are well-known, conventional steps inherent to the use of any Error Correction Code (ECC) system. A person of ordinary skill in the art would understand that the purpose of generating and storing parity data is not merely to detect errors but to correct them, and writing the corrected data back to memory is a fundamental part of this process. The implementation of this full ECC logic is a standard and predictable practice in the memory art to ensure data integrity (see MPEP § 2141.02).Therefore, it would have been obvious to apply this conventional and well-known ECC methodology to the memory system taught by D1 and D2. The claimed method represents nothing more than the predictable use of the obvious device for its intended purpose, employing standard techniques known in the art.
Claim 4: D1 and D2 teach the operation method of the memory device according to claim 3, but fail to teach that configuration bits of the information bit are not stored in successive physical addresses. However, this limitation describes a standard memory management technique known as data scrambling or address interleaving. This is a well-known practice in the art of memory design, including NAND flash memory (the primary array in D1), used to mitigate several issues:
Wear Leveling: To prevent specific, frequently written physical blocks from wearing out before others.
Error Mitigation: To prevent a single physical defect or disturbance from corrupting multiple consecutive bits of a logical data word.
Security: To obscure data patterns.
Since D1 uses a conventional NAND flash array as its primary storage, a person of ordinary skill in the art would have been motivated to implement standard NAND flash management techniques, such as avoiding successive physical addresses for logical data, to improve reliability and endurance. This is a routine design choice and optimization, the application of which would have been obvious.
Claim 5: D1 and D2 teach the operation method of the memory device according to claim 3, but fail to teach that configuration bits of the check bit are not stored in successive physical addresses. For the same reasons stated in the rejection of claim 4, managing the physical storage location of data (including parity/check bits) to avoid successive addresses is a standard and obvious memory management technique. Storing check bits in a non-successive manner would be an obvious strategy to prevent a single local defect in the parity memory device (e.g., a ReRAM array) from corrupting multiple check bits and crippling the ECC correction capability. The application of this known technique to the parity data in the obvious system of D1 and D2 would have been a routine and predictable design choice for a person of ordinary skill in the art seeking to enhance the robustness of the memory system.
As per claim 7, the claim 7 recites a method of operating a memory device comprising the steps of generating a check bit, storing information and check bits in separate memory portions, performing arithmetic processing (error detection) on them, correcting errors based on the result, and storing the corrected bits. As established in the rejection of claims 1 and 3, the memory device itself and its core method of operation would have been obvious over D1 in view of D2. D1 teaches the controller (8) generating parity data (check bits) for user data (information bits), writing the user data to the primary array (first memory portion), and writing the parity data to a separate parity memory device (second memory portion) ([0068], [0071]). The reference also teaches reading both to "verify" the data ([0037]), which inherently requires the "arithmetic processing" of error detection. The steps of "correcting an error" and storing the corrected bits are well-known, conventional steps inherent to the use of any Error Correction Code (ECC) system. Applying this full ECC methodology to the obvious memory system of D1 and D2 is a predictable use of the device for its intended purpose, employing standard techniques known in the art.
Claim 8: D1 and D2 teach the operation method of a memory device according to claim 7, but fail to teach that configuration bits of the information bit are not stored in successive physical addresses. However, This limitation describes a standard memory management technique (e.g., data scrambling or address interleaving) used to mitigate wear and errors in memory arrays like the NAND flash taught in D1. Its application to the primary storage array would have been an obvious and routine design choice for a person of ordinary skill in the art.
Claim 9: D1 and D2 teach the operation method of a memory device according to claim 7 but fail to teach that configuration bits of the check bit are not stored in successive physical addresses. For the same reasons stated in the rejection of claim 8, managing the physical storage location of parity/check bits to avoid successive addresses is a standard and obvious memory management technique. Applying this known technique to the parity data in the obvious system of D1 and D2 would have been a predictable choice to enhance system robustness.
As per claim 11, the claimed features are rejected similarly to claim 3 above.
As per claim 12, the claimed features rejected similarly to claim 7 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 2/20/2026