DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,002,705 B2 (hereinafter ‘705). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Claim 1
Claim 1 of ‘705
A method for forming a sacrificial fill material, comprising:
A method for forming a sacrificial fill material, comprising:
performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a bottom portion of the opening while preserving the oxide layer on sidewalls of the opening,
performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a bottom portion of the opening while preserving the oxide layer on sidewalls of the opening,
and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening; and epitaxially growing the sacrificial fill material in the opening using a bottom-up fill process by flowing a hydrogen chloride gas.
and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening; and epitaxially growing the sacrificial fill material in the opening using a bottom-up fill process by flowing a hydrogen chloride gas
at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.
Claim 1 of ‘705 encompasses the entirety of claim 1.
Claim 2
Claim 2 of ‘705
The method of claim 1, wherein the sacrificial fill material is silicon, silicon germanium, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or hafnium oxide.
The method of claim 1, wherein the sacrificial fill material is silicon, silicon germanium, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or hafnium oxide.
Claim 3
Claim 3 of ‘705
The method of claim 2, wherein the silicon or the silicon germanium contains a dopant of boron, phosphorous, carbon, oxygen, or antimony.
The method of claim 2, wherein the silicon or the silicon germanium contains a dopant of boron, phosphorous, carbon, oxygen, or antimony.
Claim 4
Claim 4 of ‘705
The method of claim 2, wherein the sacrificial fill material is SiGe0.4.
The method of claim 2, wherein the sacrificial fill material is SiGe0.4.
Claim 5
Claim 5 of ‘705
The method of claim 1, further comprising: epitaxially growing the sacrificial fill material using a selective epitaxial growth process with a selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material.
The method of claim 1, further comprising: epitaxially growing the sacrificial fill material using a selective epitaxial growth process with a selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material.
Claim 6
Claim 6 of ‘705
The method of claim 5, wherein the selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material is approximately 4:1 and greater.
The method of claim 5, wherein the selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material is approximately 4:1 and greater.
Claim 7
Claim 7 of ‘705
The method of claim 1 performed in an integrated cluster tool without an air break or intermediate wet preclean process.
The method of claim 1 performed in an integrated cluster tool without an air break or intermediate wet preclean process.
Claim 8
Claim 8 of ‘705
The method of claim 1, wherein the rate of the hydrogen chloride gas is flowed at a rate of approximately 60 sccm or greater
The method of claim 1, wherein the rate of the hydrogen chloride gas is approximately 70 sccm.
Claim 9
Claim 9 of ‘705
The method of claim 1 performed in a process to form a backside power via for a transistor structure.
The method of claim 1 performed in a process to form a backside power via for a transistor structure.
Claim 10
Claim 10 of ‘705
The method of claim 1, further comprising: forming a self-aligned epitaxial source/drain structure of a transistor on the sacrificial fill material.
The method of claim 1, further comprising: forming a self-aligned epitaxial source/drain structure of a transistor on the sacrificial fill material.
Claim 11
Claim 11 of ‘705
A method of forming a backside power rail contact for a source/drain epitaxial (Epi) structure of a transistor, comprising:
A method of forming a backside power rail contact for a source/drain epitaxial (Epi) structure of a transistor, comprising:
forming an opening in a substrate; depositing a conformal layer of oxide on the substrate and in the opening;
forming an opening in a substrate; depositing a conformal layer of oxide on the substrate and in the opening;
performing an etching process on the substrate and the opening, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the conformal layer of oxide from a bottom portion of the opening while preserving the oxide layer on sidewalls of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening;
performing an etching process on the substrate and the opening, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the conformal layer of oxide from a bottom portion of the opening while preserving the oxide layer on sidewalls of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening;
epitaxially growing a sacrificial fill material in the opening using a bottom-up fill process by flowing a hydrogen chloride gas;
epitaxially growing a sacrificial fill material in the opening using a bottom-up fill process by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr;
forming a source/drain Epi structure on the sacrificial fill material;
forming a source/drain Epi structure on the sacrificial fill material;
forming a gate material on the source/drain Epi structure;
forming a gate material on the source/drain Epi structure;
forming at least one interconnect signal lines above the gate material;
forming at least one interconnect signal lines above the gate material;
flipping the substrate to reveal a backside of the substrate;
flipping the substrate to reveal a backside of the substrate;
removing material of the substrate to expose the sacrificial fill material;
removing material of the substrate to expose the sacrificial fill material;
selectively etching the sacrificial fill material to remove the sacrificial fill material;
selectively etching the sacrificial fill material to remove the sacrificial fill material;
and forming the backside power rail contact which is self-aligned to the source/drain Epi structure.
and forming the backside power rail contact which is self-aligned to the source/drain Epi structure.
All elements of claim 11 are encompassed by claim 11 of ‘705
Claim 12
Claim 12 of ‘705
The method of claim 11, wherein the sacrificial fill material is silicon germanium (SiGe).
The method of claim 11, wherein the sacrificial fill material is silicon germanium (SiGe).
Claim 13
Claim 13 of ‘705
The method of claim 11, further comprising: epitaxially growing the sacrificial fill material using a selective epitaxial growth process with a selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material.
The method of claim 11, further comprising: epitaxially growing the sacrificial fill material using a selective epitaxial growth process with a selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material.
Claim 14
Claim 14 of ‘705
The method of claim 13, wherein the selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material is approximately 4:1 and greater.
The method of claim 13, wherein the selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material is approximately 4:1 and greater.
Claim 15
Claim 15 of ‘705
The method of claim 11, wherein the conformal layer of oxide is an aluminum oxide material.
The method of claim 11, wherein the conformal layer of oxide is an aluminum oxide material.
Claim 16
Claim 16 of ‘705
The method of claim 11, wherein the hydrogen chloride gas is flowed at a rate of approximately 60 sccm or greater.
The method of claim 11, wherein the rate of the hydrogen chloride gas is approximately 70 sccm.
Claim 17
Claim 17 of ‘705
A non-transitory, computer readable medium having instructions stored thereon that, when executed, cause a method for forming a sacrificial fill material to be performed, the method comprising:
A non-transitory, computer readable medium having instructions stored thereon that, when executed, cause a method for forming a sacrificial fill material to be performed, the method comprising:
performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas that removes the oxide layer from a bottom portion of the opening while preserving the oxide layer on sidewalls of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening;
performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas that removes the oxide layer from a bottom portion of the opening while preserving the oxide layer on sidewalls of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening;
and epitaxially growing the sacrificial fill material in the opening using a bottom-up fill process by flowing a hydrogen chloride gas.
and epitaxially growing the sacrificial fill material in the opening using a bottom-up fill process by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.
All elements of claim 17 are encompassed by claim 17 of ‘705
Claim 18
Claim 18 of ‘705
The non-transitory, computer readable medium of claim 17, the method further comprising: epitaxially growing the sacrificial fill material using a selective epitaxial growth process with a selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material and wherein the selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material is approximately 4:1 and greater.
The non-transitory, computer readable medium of claim 17, the method further comprising: epitaxially growing the sacrificial fill material using a selective epitaxial growth process with a selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material and wherein the selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material is approximately 4:1 and greater.
Claim 19
Claim 19 of ‘705
The non-transitory, computer readable medium of claim 17, wherein the method is performed in an integrated cluster tool without an air break or intermediate wet preclean process or wherein the method is performed in a process to form a backside power via for a transistor structure.
The non-transitory, computer readable medium of claim 17, wherein the rate of the hydrogen chloride gas is approximately 70 sccm, wherein the method is performed in an integrated cluster tool without an air break or intermediate wet preclean process, or wherein the method is performed in a process to form a backside power via for a transistor structure.
Claim 20
Claim 20 of ‘705
The non-transitory, computer readable medium of claim 17, the method further comprising: forming a self-aligned epitaxial source/drain structure of a transistor on the sacrificial fill material.
The non-transitory, computer readable medium of claim 17, the method further comprising: forming a self-aligned epitaxial source/drain structure of a transistor on the sacrificial fill material.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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