DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 1A-1C, 2A-2C, 4A-4B, 4D-4E, 5A-5B, and 6 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 11-14 are objected to because of the following informalities:
Claim 11 recites “a High Voltage Complementary Metal-Oxide- Semiconductor (HV-CMOS) sensor according to claim 1” which should be replaced with “the HV-CMOS sensor according to claim 1” to avoid antecedent bases issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6-7 and 14-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention
Claim 6 (claim 14) recites limitation “the set of HV bias contacts”. There is insufficient antecedent basis for this limitation in the claim because it is unclear whether “the set of HV bias contacts” relates back to “a set of contacts” recited in claim 1 or to set forth an additional set of HV bias contacts. For compact prosecution, the limitation “the set of HV bias contacts” is interpreted as “the set of contacts” defined in claim 1.
Claim 6 (claim 14) recites limitation “the first HV bias contact”. There is insufficient antecedent basis for this limitation in the claim because it is unclear whether “the first HV bias contact” relates back to “an HV bias contact” recited in claim 1 or to set forth an additional first HV bias contact. For compact prosecution, the limitation “the first HV bias contact” is interpreted as “the HV bias contact” defined in claim 1
Claim 15 recites the limitation “a topside" and “a backside” twice. It is unclear whether the second recited “a topside” and the second recited “a backside” intended to relate back to a previously recited “a topside” (line 3) and “a backside” (line 3) or to set forth an additional topside and an additional backside.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, 8, 10-12, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Radiation hard DMAPS pixel sensors in 150 nm CMOS technology for operation at LHC”, 2020 JINST 15 P05013 to Barbero et al. (cited in IDS of 08/05/2024, hereinafter Barbero).
With respect to claim 1, Barbero discloses a High Voltage Complementary Metal-Oxide-Semiconductor (HV-CMOS) sensor (Barbero, Figs. 1, 8, Abstract, pp. 1-11) comprising:
a p-substrate (e.g., P-substrate) (Barbero, Figs. 1, 8, Abstract, pp. 2-3) having:
a topside (e.g., a topside of the P-substrate) (Barbero, Fig. 1, pp. 2-3), and
a backside (e.g., a backside of the P-substrate) (Barbero, Fig. 1, pp. 2-3);
wherein the topside comprises:
an array of mutually spaced apart pixel structures (e.g., 129 x 36 pixels) (Barbero, Fig. 1, pp. 2-3, p. 8), including:
a first pixel structure, therein and/or thereon, wherein the first pixel structure comprises:
a set of PMOS (e.g., in the n-well NW) (Barbero, Fig. 1, pp. 2-3) and NMOS transistors (e.g., in the p-well PW), including:
a first PMOS transistor having an n-well (SN) layer (NW), and
a first NMOS transistor having:
a p-well (SP) layer (PW);
a deep n-well (DN) structure having a DN layer (DNW) (Barbero, Fig. 1, pp. 2-3);
a p-type buried (BP) layer (e.g., PSUB) disposed to mutually isolate the SN layer (NW) and the DN layer (DNW);
an n-type buried (NISO) layer (Barbero, Fig. 1, pp. 2-3) providing a SN/BN/DN stack (NW/NISO/DNW); and
a set of contacts, including a first contact (e.g., a collection node to bias n-well structures DNW/NISO/NW that is electrically coupled to the DNW layer that collects charges) (Barbero, Figs. 1, 8, p. 11), electrically coupled to the DN layer via the SN/BN/DN stack;
wherein the backside comprises:
a doped p+ layer (Barbero, Fig. 1, pp. 2-3) therein and/or thereon; and
wherein the sensor comprises an HV bias contact (e.g., a bias from the backside with a bias voltage higher than 200V) (Barbero, Fig. 1, p. 3) electrically coupled only to the p+ layer, for backside biasing thereof.
Regarding claim 4, Barbero discloses the sensor according to claim 1. Further, Barbero discloses the sensor, wherein the array of mutually spaced apart pixel structures includes N mutually spaced apart pixel structures, wherein N is a natural number greater than 2 (e.g., an array of 129 x 36 pixels) (Barbero, Fig. 1, p. 8).
Regarding claim 5, Barbero discloses the sensor according to claim 1. Further, Barbero discloses the sensor, wherein the p-substrate has a thickness in a range from 25 mm to 500 mm (e.g., of 100 mm) (Barbero, Fig. 1, p. 3). Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Regarding claim 8, Barbero discloses the sensor according to claim 1. Further, Barbero discloses the sensor, wherein the first pixel structure has a width in a range from 25 mm to 1000 mm, and/or wherein the first pixel structure has a length in a range from 25 mm to 1000 mm (e.g., pixel size 50 mm x 250 mm) (Barbero, Fig. 1, p. 4). Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Regarding claim 10, Barbero discloses the sensor according to claim 1. Further, Barbero discloses the sensor, wherein the HV bias contact is a single HV bias contact (e.g., a HV bias is provided only from the backside with a bias voltage higher than 200V) (Barbero, Fig. 1, p. 3).
Regarding claim 11, Barbero discloses a method of sensing radiation using a High Voltage Complementary Metal-Oxide-Semiconductor (HV-CMOS) sensor according to claim 1, the method comprising: applying a voltage (e.g., 1.8 V) (Barbero, Figs. 1, 8, p. 3, p. 11) to the set of contacts, including the first contact, electrically coupled to the DN layer via the SN/BN/DN stack of the first pixel structure; backside biasing (> 200V) the sensor via the HV bias contact electrically coupled only to the p+ layer; and sensing the charged particles.
Regarding claim 12, Barbero discloses the method according to claim 11. Further, Barbero discloses the method comprising irradiating the sensor at a 1 MeV neutron equivalent fluence in a range from 1 x1014 neqcm-2 to 1 x 1018neqcm-2 (e.g., in a range of 1 x1014 neqcm-2 to 1 x 1015neqcm-2) (Barbero, Abstract, Fig. 10, pp. 2, 10, 12). Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
With respect to claim 15, Barbero discloses a method of fabricating a High Voltage Complementary Metal-Oxide-Semiconductor (HV-CMOS) sensor (Barbero, Figs. 1, 8, Abstract, pp. 1-11), the method comprising:
obtaining a p-substrate (e.g., P-substrate) (Barbero, Figs. 1, 8, Abstract, pp. 2-3) having a topside (e.g., a topside of the P-substrate) (Barbero, Fig. 1, pp. 2-3) and a backside (e.g., a backside of the P-substrate) (Barbero, Fig. 1, pp. 2-3);
providing a topside of the p-substrate, comprising:
forming an array of mutually spaced apart pixel structures (e.g., 129 x 36 pixels) (Barbero, Fig. 1, pp. 2-3, p. 8), including a first pixel structure, therein and/or thereon,
wherein the first pixel structure comprises:
a set of PMOS (e.g., in the n-well NW) (Barbero, Fig. 1, pp. 2-3) and NMOS transistors (e.g., in the p-well PW), including:
a first PMOS transistor having an n-well (SN) layer (NW), and
a first NMOS transistor having:
a p-well (SP) layer (PW);
a deep n-well (DN) structure having a DN layer (DNW) (Barbero, Fig. 1, pp. 2-3);
a p-type buried (BP) layer (e.g., PSUB) disposed to mutually isolate the SN layer (NW) and the DN layer (DNW);
an n-type buried (NISO) layer (Barbero, Fig. 1, pp. 2-3) providing a SN/BN/DN stack (NW/NISO/DNW); and
a set of contacts, including a first contact (e.g., a collection node to bias n-well structures DNW/NISO/NW that is electrically coupled to the DNW layer that collects charges) (Barbero, Figs. 1, 8, p. 11), electrically coupled to the DN layer via the SN/BN/DN stack;
providing a backside of the p-substrate, comprising doping the p-substrate, thereby providing doped p+ layer (Barbero, Fig. 1, pp. 2-3) therein and/or thereon; and
electrically coupling an HV bias contact (e.g., a bias from the backside with a bias voltage higher than 200V) (Barbero, Fig. 1, p. 3) only to the p+ layer, for backside biasing thereof.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0288026 to von Kaenel in view of Barbero (“Radiation hard DMAPS pixel sensors in 150 nm CMOS technology for operation at LHC”, 2020 JINST 15 P05013).
With respect to claim 1, von Kaenel discloses a Complementary Metal-Oxide-Semiconductor (CMOS) sensor (e.g., CMOS pixel detector for electromagnetic radiation including high-energy X-ray radiation) (von Kaenel, Figs. 2F, 3B, ¶0002, ¶0013-¶0021, ¶0063-¶0067, ¶0089-¶0092, ¶0121) comprising:
a p-substrate (302’/303’/305’) (von Kaenel, Fig. 2F, ¶0090) having:
a topside (e.g., a topside of the p-doped substrate layer 306’) (von Kaenel, Fig. 2F, ¶0090), and
a backside (e.g., a backside of the p-doped substrate layer 326’) (von Kaenel, Fig. 2F, ¶0091);
wherein the topside comprises:
an array of mutually spaced apart pixel structures (e.g., an array of pixels in Fig. 3B configured as in embodiment of Fig. 2F) (von Kaenel, Fig. 3B, ¶0121), including:
a first pixel structure, therein and/or thereon, wherein the first pixel structure comprises:
a set of PMOS (e.g., in the n-well 317’) (von Kaenel, Fig. 2F, ¶0090) and NMOS transistors (e.g., in the p-well 319’), including:
a first PMOS transistor having an n-well (SN) layer (317’), and
a first NMOS transistor having:
a p-well (SP) layer (319’);
a deep n-well (DN) structure having a DN layer (312’) (von Kaenel, Fig. 2F, ¶0090);
a p-type buried (BP) layer (e.g., 306’ under the N-well 317’ and the P-well 319) disposed to mutually isolate the SN layer (317’) and the DN layer (312’);
an n-type buried (BN) layer (e.g., an n-type layer 310’, adjacent to the ohmic contact 322’) (von Kaenel, Fig. 2F, ¶0090) providing a SN/BN/DN stack (310’/312’); and
wherein the backside comprises:
a doped p+ layer (326’) (von Kaenel, Fig. 2F, ¶0091) therein and/or thereon; and
wherein the sensor comprises an HV bias contact (316’) (von Kaenel, Fig. 2F, ¶0091) electrically coupled only to the p+ layer (326’), for backside biasing thereof (e.g., a bias above the breakdown voltage is applied to a back contact 316’) (von Kaenel, Fig. 2F, ¶0091).
Further, von Kaenel does not specifically disclose a high voltage CMOS (HV-CMOS) sensor comprising: a set of contacts, including a first contact, electrically coupled to the DN layer via the SN/BN/DN stack.
However, von Kaenel teaches that the n-type buried well (310’) connected to the deep n-well (312’) serves as a charge collector (von Kaenel, Fig. 2F, ¶0090). Further, Barbero teaches forming a high voltage CMOS (HV-CMOS) pixel detector (Barbero, Figs. 1, 8, pp. 2-3, p.11) comprising a set of contacts including a first contact as a collection node to bias n-well structures (DNW/NISO/NW) that is electrically coupled to the DNW layer that collects charges, to provide CMOS sensor with enhanced capabilities for high energy particle detection.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the CMOS sensor of von Kaenel by forming a plurality of contacts including a connection node for high energy particle detectors as taught by Barbero to have a high voltage CMOS (HV-CMOS) sensor comprising: a set of contacts, including a first contact, electrically coupled to the DN layer via the SN/BN/DN stack, in order to provide HV-CMOS sensor with enhanced capabilities for high energy particle detection (Barbero, Abstract, pp. 2-3, p. 11).
Regarding claims 2 and 5, von Kaenel in view of Barbero discloses the sensor according to claim 1. Further, von Kaenel does not specifically disclose the sensor, wherein a distance through the p-substrate between the doped p+ layer and the DN layer is in a range from 20 mm to 500 mm (as claimed in claim 2); wherein the p-substrate has a thickness in a range from 25 mm to 500 mm (as claimed in claim 5).
However, von Kaenel teaches that the thickness and material used for the sensor strongly depends on the energy of the electromagnetic radiation which is to be detected (von Kaenel, Fig. 2F, ¶0063). For example, Si sensor with thickness of about 3.9, 334, and 2330 mm absorbs 90% of incident photons with energies of 2, 10 and 20 keV, respectively (von Kaenel, Fig. 2F, ¶0064).
Further, Barbero teaches forming a thin CMOS sensor of about 100 mm using high-resistivity wafer and biased from the backside for high energy radiation including proton, neutron, and hard X-ray radiation (Barbero, Abstract, pp. 1-11).
Thus, von Kaenel recognizes that the thickness and material used for the sensor impacts sensing capability of the sensor. Further, Barbero recognizes that the thickness and resistivity of the sensor substrate impact sensing capability of the sensor for high energy radiation. Thus, the thickness and material of the sensor substrate are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the thickness and material of the sensor substrate as von Kaenel and Barbero have identified the thickness and material of the sensor substrate as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific thickness of the sensor substrate such that a distance through the p-substrate between the doped p+ layer and the DN layer is in a range from 20 mm to 500 mm, and wherein the p-substrate has a thickness in a range from 25 mm to 500 mm in order to provide CMOS sensor with enhanced capabilities and suitable for electromagnetic and high energy radiation detection as taught by von Kaenel (¶0063-¶0064) and Barbero (Abstract, pp. 1-11) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the CMOS sensor of von Kaenel/Barbero by optimizing the thickness and material of the sensor substrate as taught by von Kaenel, wherein the CMOS sensor has specific resistivity of the sensor wafer as taught by Barbero to have the sensor, wherein a distance through the p-substrate between the doped p+ layer and the DN layer is in a range from 20 mm to 500 mm (as claimed in claim 2); wherein the p-substrate has a thickness in a range from 25 mm to 500 mm (as claimed in claim 5), in order to provide monolithic CMOS integrated pixel detector for electromagnetic radiation, with enhanced capabilities, and suitable and high energy radiation detection (von Kaenel, ¶0013-¶0020, ¶0063-¶0064; Barbero, Abstract, pp. 1-11).
Regarding claims 3 and 8, von Kaenel in view of Barbero discloses the sensor according to claim 1. Further, von Kaenel does not specifically disclose the sensor, wherein the array of mutually spaced apart pixel structures includes a second pixel structure and wherein the respective first contacts of the first pixel structure and the second pixel structure are mutually spaced apart by a spacing in a range from 1 mm to 20 mm (as claimed in claim 3); wherein the first pixel structure has a width in a range from 25 mm to 1000 mm, and/or wherein the first pixel structure has a length in a range from 25 mm to 1000 mm (as claimed in claim 8).
However, von Kaenel teaches that the detector pixels are defined by the charge collectors (310’) having width between 0.1-2 mm the thickness to isolate pixels, and the pixel size (313’) is defined by a distance between the charge collectors (310’) which varies in a range between 100-200 mm, or 2-40 mm (von Kaenel, Fig. 2F, ¶0010, ¶0090). The pixel size depends on the CMOS process used for the specific radiation detection and material used for the sensor (von Kaenel, Fig. 2F, ¶0010, ¶0063), and the isolation of the pixels depends on the width of the charge collectors.
Further, Barbero teaches forming a thin CMOS sensor having pixel size of about 40 mm x 250 mm for high energy radiation including proton, neutron, and hard X-ray radiation (Barbero, Abstract, pp. 1-11).
Thus, von Kaenel recognizes that CMOS process and material used for the sensor define the size of the pixels and the spacing between the pixels and impacts sensing capability of the sensor. Further, Barbero recognizes that the size of the pixel impacts sensing capability of the CMOS sensor for high energy radiation. Thus, CMOS process and material used for the sensor are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, CMOS process and material of the sensor substrate for specific radiation detection as von Kaenel and Barbero have identified CMOS process and material of the sensor substrate for specific radiation detection as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific size of the pixels and the spacing between the pixels such that the respective first contacts of the first pixel structure and the second pixel structure are mutually spaced apart by a spacing in a range from 1 mm to 20 mm; wherein the first pixel structure has a width in a range from 25 mm to 1000 mm, and/or wherein the first pixel structure has a length in a range from 25 mm to 1000 mm, in order to provide CMOS sensor with enhanced capabilities and suitable for electromagnetic and high energy radiation detection as taught by von Kaenel (¶0063-¶0064) and Barbero (Abstract, pp. 1-11) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the CMOS sensor of von Kaenel/Barbero by optimizing CMOS process and material of the sensor substrate as taught by von Kaenel and Barbero to have the sensor, wherein the array of mutually spaced apart pixel structures includes a second pixel structure and wherein the respective first contacts of the first pixel structure and the second pixel structure are mutually spaced apart by a spacing in a range from 1 mm to 20 mm (as claimed in claim 3); wherein the first pixel structure has a width in a range from 25 mm to 1000 mm, and/or wherein the first pixel structure has a length in a range from 25 mm to 1000 mm (as claimed in claim 8), in order to provide monolithic CMOS integrated pixel detector for electromagnetic radiation, with enhanced capabilities, and suitable and high energy radiation detection (von Kaenel, ¶0010, ¶0013-¶0020, ¶0063-¶0064, ¶0090-¶0091; Barbero, Abstract, pp. 1-11).
Regarding claim 4, von Kaenel in view of Barbero discloses the sensor according to claim 1. Further, von Kaenel discloses the sensor, wherein the array of mutually spaced apart pixel structures includes N mutually spaced apart pixel structures, wherein N is a natural number greater than 2 (e.g., an array of pixels in Fig. 3B configured as in embodiment of Fig. 2F) (von Kaenel, Fig. 3B, ¶0121).
Regarding claim 6, von Kaenel in view of Barbero discloses the sensor according to claim 1. Further, von Kaenel discloses the sensor, wherein the backside comprises a metallized layer (316’, metal back contact) (von Kaenel, Fig. 2F, ¶0090-¶0091) overlaying the doped p+ layer (326’), wherein the set of bias contacts, including the first HV bias contact (e.g., a bias above the breakdown voltage is applied to a back contact 316’) (von Kaenel, Fig. 2F, ¶0091), is electrically coupled only to the p+ layer (326’) via the metallized layer.
Regarding claim 7, von Kaenel in view of Barbero discloses the sensor according to claim 6. Further, von Kaenel does not specifically disclose the sensor, wherein the metallized layer comprises and/or is a grid.
However, von Kaenel teaches an embodiment of Fig. 2H, wherein the back contact includes the metallization layer (1916) provided only on a small fraction of the pixel backside to minimize the blocking of electromagnetic radiation (von Kaenel, Fig. 2H, ¶0099).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the CMOS sensor of von Kaenel/Barbero by forming a backside contact on a small fraction of the pixel backside as taught by von Kaenel to have the sensor, wherein the metallized layer comprises and/or is a grid, in order to minimize the blocking of electromagnetic radiation (von Kaenel, Fig. 2H, ¶0099).
Regarding claim 9, von Kaenel in view of Barbero discloses the sensor according to claim 1. Further, von Kaenel discloses the sensor, wherein the HV bias contact (316’) extends over the backside (e.g., over entire pixel (100%) having width 313’, as in Fig. 2F) (von Kaenel, Fig. 2F, ¶0090-¶0091), for example in a range from 25% to 100%.
Regarding claim 10, von Kaenel in view of Barbero discloses the sensor according to claim 1. Further, von Kaenel discloses the sensor, wherein the HV bias contact (316’) (von Kaenel, Fig. 2F, ¶0090-¶0091) is a single HV bias contact (e.g., a bias above the breakdown voltage is applied only to a back contact 316’) (von Kaenel, Fig. 2F, ¶0091).
Regarding claim 11, von Kaenel in view of Barbero discloses a method of sensing radiation using a High Voltage Complementary Metal-Oxide-Semiconductor (HV-CMOS) sensor according to claim 1, the method comprising: backside biasing the sensor via the HV bias contact (e.g., a bias above the breakdown voltage is applied only to a back contact 316’) (von Kaenel, Fig. 2F, ¶0091) electrically coupled only to the p+ layer (326’), but does not specifically disclose a method of sensing charged particles by applying a voltage to the set of contacts, including the first contact, electrically coupled to the DN layer via the SN/BN/DN stack of the first pixel structure; and sensing the charged particles.
However, Barbero teaches a method of sensing charged particles (Barbero, Figs. 1, 8, Abstract, pp. 1-11) by applying a voltage (e.g., 1.8 V) (Barbero, Figs. 1, 8, p. 3, p. 11) to the set of contacts, including the first contact, electrically coupled to the DN layer via the SN/BN/DN stack of the first pixel structure; backside biasing (> 200V) the sensor via the HV bias contact electrically coupled only to the p+ layer; and sensing the charged particles.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the CMOS sensor of von Kaenel/Barbero by sensing high energy charge particles as taught by Barbero to have a method of sensing charged particles by applying a voltage to the set of contacts, including the first contact, electrically coupled to the DN layer via the SN/BN/DN stack of the first pixel structure; and sensing the charged particles, in order to provide monolithic CMOS integrated pixel detector with enhanced capabilities and suitable and high energy radiation detection (Barbero, Abstract, pp. 1-11).
Regarding claim 12, von Kaenel in view of Barbero discloses the method according to claim 11. Further, von Kaenel does not specifically disclose the method comprising irradiating the sensor at a 1 MeV neutron equivalent fluence in a range from 1 x1014 neqcm-2 to 1 x 1018neqcm-2.
However, Barbero teaches the method comprising irradiating the HV-CMOS sensor at a 1 MeV neutron equivalent fluence in a range from 1 x1014 neqcm-2 to 1 x 1015neqcm-2 (Barbero, Abstract, Fig. 10, pp. 2, 10, 12).
Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the CMOS sensor of von Kaenel/Barbero by sensing high energy charge particles as taught by Barbero to have the method comprising irradiating the sensor at a 1 MeV neutron equivalent fluence in a range from 1 x1014 neqcm-2 to 1 x 1018neqcm-2, in order to provide monolithic CMOS integrated pixel detector with enhanced capabilities and suitable and high energy radiation detection (Barbero, Abstract, pp. 1-11).
Regarding claim 14, von Kaenel in view of Barbero discloses the method according to claim 11. Further, von Kaenel does not specifically disclose the method wherein backside biasing the sensor via the HV bias contact electrically coupled only to the p+ layer comprises: backside biasing the sensor via the set of HV bias contacts, including the first HV bias contact, electrically coupled only to the p+ layer at a voltage in a range from 200 V to 950 V.
However, Barbero teaches the method wherein backside biasing the sensor via the HV bias contact electrically coupled only to the p+ layer comprises: backside biasing the sensor via the set of bias contacts (Barbero, Figs. 1, 8, p. 11), including the first HV bias contact, electrically coupled only to the p+ layer at a voltage higher than 200 V (Barbero, Abstract, pp. 1-11).
The claimed range overlaps the range of Barbero. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of von Kaenel/Barbero by biasing the sensor for sensing high energy particles as taught by Barbero to have the method, wherein backside biasing the sensor via the HV bias contact electrically coupled only to the p+ layer comprises: backside biasing the sensor via the set of HV bias contacts, including the first HV bias contact, electrically coupled only to the p+ layer at a voltage in a range from 200 V to 950 V, in order to provide monolithic CMOS integrated pixel detector with enhanced capabilities and suitable and high energy radiation detection (Barbero, Abstract, pp. 1-11).
With respect to claim 15, von Kaenel discloses a method of fabricating a High Voltage Complementary Metal-Oxide-Semiconductor (HV-CMOS) sensor (e.g., CMOS pixel detector for electromagnetic radiation including high-energy X-ray radiation) (von Kaenel, Figs. 2F, 3B, ¶0002, ¶0013-¶0021, ¶0063-¶0067, ¶0089-¶0092, ¶0121), the method comprising:
obtaining a p-substrate (302’/303’/305’) (von Kaenel, Fig. 2F, ¶0090) having a topside (e.g., a topside of the p-doped substrate layer 306’) (von Kaenel, Fig. 2F, ¶0090) and a backside (e.g., a backside of the p-doped substrate layer 326’) (von Kaenel, Fig. 2F, ¶0091);
providing a topside of the p-substrate (302’/303’/305’), comprising:
forming an array of mutually spaced apart pixel structures (e.g., an array of pixels in Fig. 3B configured as in embodiment of Fig. 2F) (von Kaenel, Fig. 3B, ¶0121), including a first pixel structure, therein and/or thereon,
wherein the first pixel structure comprises:
a set of PMOS (e.g., in the n-well 317’) (von Kaenel, Fig. 2F, ¶0090) and NMOS transistors (e.g., in the p-well 319’), including:
a first PMOS transistor having an n-well (SN) layer (317’), and
a first NMOS transistor having:
a p-well (SP) layer (319’);
a deep n-well (DN) structure having a DN layer (312’) (von Kaenel, Fig. 2F, ¶0090);
a p-type buried (BP) layer (e.g., 306’ under the N-well 317’ and the P-well 319) disposed to mutually isolate the SN layer (317’) and the DN layer (312’);
an n-type buried (BN) layer (e.g., an n-type layer 310’, adjacent to the ohmic contact 322’) (von Kaenel, Fig. 2F, ¶0090) providing a SN/BN/DN stack (310’/312’); and
providing a backside of the p-substrate (302’/303’/305’), comprising doping the p-substrate (e.g., forming a doped p+ layer 326’) (von Kaenel, Fig. 2F, ¶0091), thereby providing a doped p+ layer therein and/or thereon; and
electrically coupling an HV bias contact (316’) (von Kaenel, Fig. 2F, ¶0091) only to the p+ layer (326’), for backside biasing thereof (e.g., a bias above the breakdown voltage is applied to a back contact 316’) (von Kaenel, Fig. 2F, ¶0091).
Further, von Kaenel does not specifically disclose a method of fabricating a HV-CMOS sensor, the method comprising: a set of contacts, including a first contact, electrically coupled to the DN layer via the SN/BN/DN stack.
However, von Kaenel teaches that the n-type buried well (310’) connected to the deep n-well (312’) serves as a charge collector (von Kaenel, Fig. 2F, ¶0090). Further, Barbero teaches forming a HV-CMOS pixel detector (Barbero, Figs. 1, 8, pp. 2-3, p.11) comprising a set of contacts including a first contact as a collection node to bias n-well structures (DNW/NISO/NW) that is electrically coupled to the DNW layer that collects charges, to provide CMOS sensor with enhanced capabilities for high energy particle detection.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify a method of fabricating the CMOS sensor of von Kaenel by forming a plurality of contacts including a connection node as taught by Barbero to have the method of fabricating a HV-CMOS sensor, comprising: a set of contacts, including a first contact, electrically coupled to the DN layer via the SN/BN/DN stack, in order to provide HV-CMOS sensor with enhanced capabilities for high energy particle detection (Barbero, Abstract, pp. 2-3, p. 11).
Claims 2-3, 6-7, 9, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over “Radiation hard DMAPS pixel sensors in 150 nm CMOS technology for operation at LHC”, 2020 JINST 15 P05013 to Barbero in view of von Kaenel (US 2019/0288026).
Regarding claim 2, Barbero discloses the sensor according to claim 1. Further, Barbero does not specifically disclose the sensor, wherein a distance through the p-substrate between the doped p+ layer and the DN layer is in a range from 20 mm to 500 mm.
However, von Kaenel teaches that the thickness and material used for the sensor strongly depends on the energy of the electromagnetic radiation which is to be detected (von Kaenel, Fig. 2F, ¶0063). For example, Si sensor with thickness of about 3.9, 334, and 2330 mm absorbs 90% of incident photons with energies of 2, 10 and 20 keV, respectively (von Kaenel, Fig. 2F, ¶0064).
Further, Barbero teaches forming a thin CMOS sensor of about 100 mm using high-resistivity wafer and biased from the backside for high energy radiation including proton, neutron, and hard X-ray radiation (Barbero, Abstract, pp. 1-11).
Thus, von Kaenel recognizes that the thickness and material used for the sensor impacts sensing capability of the sensor. Further, Barbero recognizes that the thickness and resistivity of the sensor substrate impact sensing capability of the sensor for high energy radiation. Thus, the thickness and material of the sensor substrate are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the thickness and material of the sensor substrate as von Kaenel and Barbero have identified the thickness and material of the sensor substrate as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific thickness of the sensor substrate such that a distance through the p-substrate between the doped p+ layer and the DN layer is in a range from 20 mm to 500 mm, in order to provide CMOS sensor with enhanced capabilities and suitable for electromagnetic and high energy radiation detection as taught by von Kaenel (¶0063-¶0064) and Barbero (Abstract, pp. 1-11) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the CMOS sensor of Barbero by optimizing the thickness and material of the sensor substrate as taught by von Kaenel, wherein the CMOS sensor has specific resistivity of the sensor wafer as taught by Barbero to have the sensor, wherein a distance through the p-substrate between the doped p+ layer and the DN layer is in a range from 20 mm to 500 mm, in order to provide monolithic CMOS integrated pixel detector for electromagnetic radiation, with enhanced capabilities, and suitable and high energy radiation detection (von Kaenel, ¶0013-¶0020, ¶0063-¶0064; Barbero, Abstract, pp. 1-11).
Regarding claim 3, Barbero discloses the sensor according to claim 1. Further, Barbero does not specifically disclose the sensor, wherein the array of mutually spaced apart pixel structures includes a second pixel structure and wherein the respective first contacts of the first pixel structure and the second pixel structure are mutually spaced apart by a spacing in a range from 1 mm to 20 mm.
However, von Kaenel teaches that the detector pixels are defined by the charge collectors (310’) having width between 0.1-2 mm the thickness to isolate pixels, and the pixel size (313’) is defined by a distance between the charge collectors (310’) which varies in a range between 100-200 mm, or 2-40 mm (von Kaenel, Fig. 2F, ¶0010, ¶0090). The pixel size depends on the CMOS process used for the specific radiation detection and material used for the sensor (von Kaenel, Fig. 2F, ¶0010, ¶0063), and the isolation of the pixels depends on the width of the charge collectors.
Further, Barbero teaches forming a thin CMOS sensor having pixel size of about 40 mm x 250 mm for high energy radiation including proton, neutron, and hard X-ray radiation (Barbero, Abstract, pp. 1-11).
Thus, von Kaenel recognizes that CMOS process and material used for the sensor define the size of the pixels and the spacing between the pixels and impacts sensing capability of the sensor. Further, Barbero recognizes that the size of the pixel impacts sensing capability of the CMOS sensor for high energy radiation. Thus, CMOS process and material used for the sensor are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, CMOS process and material of the sensor substrate for specific radiation detection as von Kaenel and Barbero have identified CMOS process and material of the sensor substrate for specific radiation detection as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific size of the pixels and the spacing between the pixels such that the respective first contacts of the first pixel structure and the second pixel structure are mutually spaced apart by a spacing in a range from 1 mm to 20 mm, in order to provide CMOS sensor with enhanced capabilities and suitable for electromagnetic and high energy radiation detection as taught by von Kaenel (¶0063-¶0064) and Barbero (Abstract, pp. 1-11) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the CMOS sensor of Barbero by optimizing CMOS process and material of the sensor substrate as taught by von Kaenel and Barbero to have the sensor, wherein the array of mutually spaced apart pixel structures includes a second pixel structure and wherein the respective first contacts of the first pixel structure and the second pixel structure are mutually spaced apart by a spacing in a range from 1 mm to 20 mm, in order to provide monolithic CMOS integrated pixel detector for electromagnetic radiation, with enhanced capabilities, and suitable and high energy radiation detection (von Kaenel, ¶0010, ¶0013-¶0020, ¶0063-¶0064, ¶0090-¶0091; Barbero, Abstract, pp. 1-11).
Regarding claims 6-7 and 9, Barbero discloses the sensor according to claim 1. Further, Barbero does not specifically disclose the sensor, wherein the backside comprises a metallized layer overlaying the doped p+ layer, wherein the set of HV bias contacts, including the first HV bias contact, is electrically coupled only to the p+ layer via the metallized layer (as claimed in claim 6); wherein the metallized layer comprises and/or is a grid (as claimed in claim 7); wherein the HV bias contact extends over the backside, for example in a range from 25% to 100% (as claimed in claim 9).
However, von Kaenel teaches forming CMOS sensor, wherein the backside comprises a metallized layer (316’, metal back contact) (von Kaenel, Fig. 2F, ¶0090-¶0091) overlaying the doped p+ layer (326’), wherein the set of bias contacts, including the first HV bias contact (e.g., a bias above the breakdown voltage is applied to a back contact 316’) (von Kaenel, Fig. 2F, ¶0091), is electrically coupled only to the p+ layer (326’) via the metallized layer, wherein the HV bias contact (316’) extends over the backside (e.g., over entire pixel (100%) having width 313’, as in Fig. 2F) (von Kaenel, Fig. 2F, ¶0090-¶0091), for example in a range from 25% to 100%.
Further, von Kaenel teaches an embodiment of Fig. 2H, wherein the back contact includes the metallization layer (1916) provided only on a small fraction of the pixel backside to minimize the blocking of electromagnetic radiation (von Kaenel, Fig. 2H, ¶0099).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the CMOS sensor of Barbero by forming a backside contact at the pixel backside as taught by von Kaenel to have the sensor, wherein the backside comprises a metallized layer overlaying the doped p+ layer, wherein the set of HV bias contacts, including the first HV bias contact, is electrically coupled only to the p+ layer via the metallized layer (as claimed in claim 6); wherein the metallized layer comprises and/or is a grid (as claimed in claim 7); wherein the HV bias contact extends over the backside, for example in a range from 25% to 100% (as claimed in claim 9), in order to provide monolithic CMOS integrated pixel detector having improved capabilities; and to minimize the blocking of electromagnetic radiation (von Kaenel, ¶0013-¶0020, ¶0063-¶0064, ¶0099).
Regarding claim 14, Barbero discloses the method according to claim 11. Further, Barbero discloses the method, wherein backside biasing the sensor via the HV bias contact electrically coupled only to the p+ layer comprises (Barbero, Abstract, pp. 1-11); backside biasing the sensor via the set of HV bias contacts, including the first HV bias contact, electrically coupled only to the p+ layer at a voltage higher than 200V, but does not specifically disclose a range from 200 V to 950 V.
However, the claimed range overlaps the range of Barbero (e.g., higher than 200V). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Barbero by biasing the sensor at a voltage in a range from 200 V to 950 V, in order to provide monolithic CMOS integrated pixel detector with enhanced capabilities and suitable and high energy radiation detection (Barbero, Abstract, pp. 1-11).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0288026 to von Kaenel in view of Barbero (“Radiation hard DMAPS pixel sensors in 150 nm CMOS technology for operation at LHC”, 2020 JINST 15 P05013) as applied to claim 12, and further in view of Tümer (US Patent No. 5,821,541).
Regarding claim 13, von Kaenel in view of Barbero discloses the method according to claim 12. Further, von Kaenel does not specifically disclose the method comprising irradiating the sensor for a time in a range from 1 year to 10 years.
However, Tümer teaches forming a silicon detector (Tümer, Col. 36, lines 63-67; Col. 37, lines 1-40; Col. 38, lines 19-55) comprising CMOS transistors capable of standing the Superconducting Super Collider (SSC) environment producing high energy particles for 10 years of exposure.
Thus, Tümer recognizes that CMOS process for front-end electronics required for the CMOS sensor impacts lifetime of the CMOS sensor. Thus, CMOS process for front-end electronics of the CMOS sensor is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, CMOS processes for front-end electronics of the CMOS sensor as Tümer has identified CMOS process for front-end electronics of the CMOS sensor as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific CMOS process for front-end electronics of the CMOS sensor such that the method comprises irradiating the sensor for a time in a range from 1 year to 10 years, in order to provide CMOS sensor with radiation hard electronic circuits and with increased lifetime in radiation hard environment as taught by Tümer (Col. 38, lines 19-55) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the CMOS sensor of von Kaenel/Barbero by optimizing CMOS process for front-end electronics of the CMOS sensor as taught by Tümer to have the method comprising irradiating the sensor for a time in a range from 1 year to 10 years, in order to provide CMOS sensor with radiation hard electronic circuits and with increased lifetime in radiation hard environment (Tümer, Col. 38, lines 19-55).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over “Radiation hard DMAPS pixel sensors in 150 nm CMOS technology for operation at LHC”, 2020 JINST 15 P05013 to Barbero in view of Tümer (US Patent No. 5,821,541).
Regarding claim 13, Barbero discloses the method according to claim 12. Further, Barbero does not specifically disclose the method comprising irradiating the sensor for a time in a range from 1 year to 10 years.
However, Tümer teaches forming a silicon detector (Tümer, Col. 36, lines 63-67; Col. 37, lines 1-40; Col. 38, lines 19-55) comprising CMOS transistors capable of standing the Superconducting Super Collider (SSC) environment producing high energy particles for 10 years of exposure.
Thus, Tümer recognizes that CMOS process for front-end electronics required for the CMOS sensor impacts lifetime of the CMOS sensor. Thus, CMOS process for front-end electronics of the CMOS sensor is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, CMOS processes for front-end electronics of the CMOS sensor as Tümer has identified CMOS process for front-end electronics of the CMOS sensor as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific CMOS process for front-end electronics of the CMOS sensor such that the method comprises irradiating the sensor for a time in a range from 1 year to 10 years, in order to provide CMOS sensor with radiation hard electronic circuits and with increased lifetime in radiation hard environment as taught by Tümer (Col. 38, lines 19-55) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the CMOS sensor of Barbero by optimizing CMOS process for front-end electronics of the CMOS sensor as taught by Tümer to have the method comprising irradiating the sensor for a time in a range from 1 year to 10 years, in order to provide CMOS sensor with radiation hard electronic circuits and with increased lifetime in radiation hard environment (Tümer, Col. 38, lines 19-55).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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