Prosecution Insights
Last updated: August 16, 2026
Application No. 18/836,354

DICING/DIE-BONDING FILM AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Non-Final OA §103
Filed
Aug 07, 2024
Priority
Feb 17, 2022 — JP PCT/JP2022/006459 +1 more
Examiner
AHMED, SHAHED
Art Unit
Tech Center
Assignee
RESONAC Corporation
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
903 granted / 995 resolved
+30.8% vs TC avg
Minimal -0% lift
Without
With
+-0.1%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
51 currently pending
Career history
1034
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
53.9%
+13.9% vs TC avg
§102
21.8%
-18.2% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 995 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is responsive to application No. 18836354 filed on 08/07/2024. Information Disclosure Statement Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered. Priority Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuyoshi et al. (WO 2021095302 A1). Regarding independent claim 1, Tsuyosho et al. teach a dicing die-bonding film comprising: a die-bonding film (Fig. 1(b), element 5); and a dicing film comprising a pressure-sensitive adhesive layer (Fig. 1(b), element 3) laminated on the die-bonding film, wherein the die-bonding film has a thickness of 10 μm or less (specification discloses thickness of 1-300 μm, “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05.μm), and the pressure-sensitive adhesive layer has a thickness of less than 10 μm (specification discloses thickness of 1-200 μm, “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP 2144.05.). Regarding claim 2, Tsuyosho et al. teach wherein a 30° peel strength of the pressure-sensitive adhesive layer against the die-bonding film is 6.0 N/25 mm or greater (Specification teaches 30° peel strength and 6.0 N / 25 mm or more). Regarding claim 3, Tsuyosho et al. teach wherein the dicing film further comprises a base material film (Fig. 1(b), element 1), and the pressure-sensitive adhesive layer is provided on the base material film (Fig. 1(b). Regarding claim 4, Tsuyosho et al. teach sticking the die-bonding film of the dicing die-bonding film according to claim 1 to a semiconductor wafer; and dividing the semiconductor wafer and the die-bonding film by a process including stretching the dicing die-bonding film, and thereby forming die-bonding film-attached chips each comprising a chip and the die-bonding film that has been singularized, on the pressure-sensitive adhesive layer ((paragraphs [0065] and [0066]) further discloses a method for producing a semiconductor device 100, including: (B) a step for stealth-dicing a wafer W; (C) a step for affixing the wafer W to the adhesive layer 5; and (D) a step for expanding the base layer 1 to obtain adhesive-backed chips 8 by individually dicing the wafer W and the adhesive layer 5). Regarding claim 5, Tsuyosho et al. teach wherein the process of dividing the semiconductor wafer and the die-bonding film is a stealth dicing process (paragraphs [0065] and [0066]) discloses B) a step for stealth-dicing a wafer W). Cited Prior Art The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAHED AHMED/ Primary Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Aug 07, 2024
Application Filed
Jul 31, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12703622
ELECTRONIC DEVICE, ELECTRONIC DEVICE MANUFACTURING APPARATUS, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE
2y 11m to grant Granted Aug 11, 2026
Patent 12696751
INTEGRATED CIRCUIT DEVICES
2y 9m to grant Granted Jul 28, 2026
Patent 12690209
SEMICONDUCTOR DEVICE FOR IMPROVING ON VOLTAGE AND SATURATION VOLTAGE
3y 6m to grant Granted Jul 21, 2026
Patent 12690301
DIODE AND MANUFACTURING METHOD THEREOF
3y 4m to grant Granted Jul 21, 2026
Patent 12690225
HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
3y 2m to grant Granted Jul 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
91%
With Interview (-0.1%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 995 resolved cases by this examiner. Grant probability derived from career allowance rate.

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