DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the preliminary amendment received on 8/12/2024. Claims 1-12 are pending in this application.
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In particular, claim 1 cites “a first transistor; a second transistor; a third transistor” & “the first electrode…overlapping..., and the second transistor” are not clear because of “third transistor”. The claim does not clearly specify a particular position of the third transistor with respect with other claimed elements, whether or not it is also being overlapped by the first electrode. For examination purpose, Figs. 3 & 4 will be applied to consider position of the third transistor.
Claims 2-11 are rejected as being dependent on claim 1.
Applicant is suggested to revise and clarify the claim(s) to avoid any further confusions.
For best understanding and examination purpose, the claim(s) will be best considered based on drawings, disclosure, and/or any applicable prior arts.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1, 2, 10 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao (US 5,994,197).
Re claim 1, Liao teaches, under BRI, Fig. 3G, cols. 6-7, a memory device comprising;
-a first transistor (304);
-a second transistor (304);
-a third transistor (304);
-a first capacitor (left); and
-a second capacitor (right);
wherein the first capacitor (left) comprises a first electrode (336) and a second electrode (318),
wherein the second capacitor (right) comprises the first electrode (336) and a third electrode (318),
wherein one of a source and a drain (308) of the first transistor is electrically connected to the second electrode (318),
wherein one of a source and a drain (308) of the second transistor is electrically connected to the third electrode (318),
wherein a gate of the third transistor (304) is electrically connected to the second electrode (318) (within the cell),
wherein the first electrode (336) comprises a portion overlapping with each of the second electrode (318), the third electrode (318), the first transistor, and the second transistor (304), and
wherein the first electrode (318) is supplied (*) with a fixed potential or a ground potential.
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(*) The limitation “…supplied with a fixed potential or ground potential” is merely a functional/intended use limitation that does not structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114. Additionally, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Re claim 2, Liao teaches, top and front views of Fig. 3G, wherein the first electrode (336) comprises a portion (middle) positioned above the first transistor (304) and a portion (left or right) on a side of the first transistor (304).
Re claim 10, Liao teaches, Fig. 3G, each of the first electrode (336) and the second electrode (318) has a flat-plate shape (tops of 318, 3336) (see also Fig. 1).
Re claim 12, Liao teaches, under BRI, Fig. 3G, cols. 6-7, a memory device comprising
-a first transistor (304);
-a second transistor (304);
-a first capacitor (left); and
-a second capacitor (right),
wherein the first capacitor (left) comprises a first electrode (336) and a second electrode (318),
wherein the second capacitor (right) comprises the first electrode (336) and a third electrode (318),
wherein one of a source and a drain (308) of the first transistor is electrically connected to the second electrode (318),
wherein one of a source and a drain (308) of the second transistor is electrically connected to the third electrode (318),
wherein a first conductive layer (336) comprising a region configured to function as the first electrode (336) comprises a portion over and overlapping with the second electrode (318), the third electrode (318), the first transistor, and the second transistor (304), and
wherein the first conductive layer (336) comprises a portion provided below the second electrode (318) and the third electrode (318).
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5. Claims 1, 11 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fazan et al. (US 6,791,131).
Re claim 1 & 11, Fazan teaches, under BRI, Fig. 18, cols. 5-8 , a memory device comprising;
-a first transistor (2nd right);
-a second transistor (3rd right);
-a third transistor (1st left);
-a first capacitor (left); and
-a second capacitor (right);
wherein the first capacitor (left) comprises a first electrode (95) and a second electrode (85),
wherein the second capacitor (right) comprises the first electrode (95) and a third electrode (85),
wherein one of a source and a drain (30) of the first transistor is electrically connected to the second electrode (85),
wherein one of a source and a drain (30) of the second transistor is electrically connected to the third electrode (85),
wherein a gate of the third transistor (1st left) is electrically connected to the second electrode (85),
wherein the first electrode (95) comprises a portion overlapping with each of the second electrode (85), the third electrode (85), the first transistor, and the second transistor (under transistors),
wherein the first electrode (95) is supplied (*) with a fixed potential or a ground potential, and
wherein a top wherein a top surface of the second electrode (85) has a depressed portion, and wherein the first electrode (95) comprises a protruding portion engaging with the top surface of the second electrode (85).
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(*) The limitation “…supplied with a fixed potential or ground potential” is merely a functional/intended use limitation that does not structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114. Additionally, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Re claim 12, Fazan teaches, under BRI, Fig. 18, cols. 5-8, a memory device comprising
-a first transistor (2nd right);
-a second transistor (3rd right);
-a first capacitor (left); and
-a second capacitor (right),
wherein the first capacitor (left) comprises a first electrode (95) and a second electrode (85),
wherein the second capacitor (right) comprises the first electrode (95) and a third electrode (85),
wherein one of a source and a drain (30) of the first transistor is electrically connected to the second electrode (85),
wherein one of a source and a drain (30) of the second transistor is electrically connected to the third electrode (318),
wherein a first conductive layer (95) comprising a region configured to function as the first electrode (95) comprises a portion over and overlapping with the second electrode (85), the third electrode (85), the first transistor, and the second transistor (under transistors), and
wherein the first conductive layer (95) comprises a portion provided below (upper parts of 85) the second electrode (85) and the third electrode (85).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 3-6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Liao in view of Atsumi et al. (US 2015/0255139).
The teachings of Liao have been discussed above.
Re claim 3, Liao does not teach a connection electrode, wherein the other of the source and the drain of the first transistor is electrically connected to the connection electrode, and wherein the other of the source and the drain of the second transistor is electrically connected to the connection electrode.
Atsumi teaches, Fig. 6, [0140, 0141], a connection electrode (plug 147j), wherein the other of the source and the drain of the first transistor (left) is electrically connected to the connection electrode (147j), and wherein the other of the source and the drain of the second transistor (middle) is electrically connected to the connection electrode (147j).
As taught by Atsumi, one of ordinary skill in the art would utilize & modify the above teaching to obtain a conduction electrode connecting to the other source and drain as claimed, because it aids in facilitating the interconnection whin the formed memory cell structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Atsumi in combination Liao due to above reason.
Re claim 4, in combination cited above, Atsumi teaches, under BRI, Fig. 6, wherein a first conductive layer (left part of 104j) is configured to function as the other of the source and the drain of the first transistor (top left),
wherein a second conductive layer (right part of 104j) is configured to function as the other of the source and the drain of the second transistor (middle), and
wherein the connection electrode (147j) comprises a portion in contact with a top surface of the first conductive layer (left part of 104j, a portion in contact with a side surface of the first conductive layer (left part of 104j), a portion in contact with a top surface of the second conductive layer (right part of 104j), and a portion in contact with a side surface of the second conductive layer (right part of 104j).
Note: in contact # directly/physically contact.
Re claim 5, in combination cited above, Atsumi teaches, under BRI, Fig. 6, a fourth transistor and a third capacitor,
wherein the fourth transistor (in third row from 500) and the third capacitor (Ca in second row from 500) are positioned below the first transistor (top left),
wherein the third capacitor (Ca) comprises a fourth electrode (151) and a fifth electrode (152),
wherein the fourth electrode (151) is supplied (*) with a ground potential or a fixed potential or aground potential,
wherein one of a source and a drain of the fourth transistor (in 3rd row) is electrically connected to the fifth electrode (151), and
wherein the other of the source and the drain of the fourth transistor (in 3rd row) is electrically connected to the connection electrode (147).
Re claim 6, in combination cited above, Atsumi teaches, Fig. 6, wherein a third conductive layer (extend to right of from 4th transistor) is configured to function as the other of the source and the drain of the fourth transistor (in 3rd row), and
wherein the connection electrode (147) comprises a portion in contact with a top surface of the third conductive layer and a portion in contact with a side surface of the third conductive layer.
Note: in contact # directly/physically contact.
Re claim 9, in combination cited above, Atsumi teaches, Figs. 6 & 7A, [0146], wherein the first transistor comprises a semiconductor layer (101) and a gate electrode (103), wherein the fourth electrode (151) comprises a portion positioned below the first transistor (upper), and wherein the gate electrode (103) comprises a portion overlapping with the fourth electrode (151) with the semiconductor layer (103) therebetween.
7. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Liao in view of Kim et al. (US 2003/0148581).
The teachings of Liao have been discussed above.
Re claim 11, Liao does not wherein a top surface of the second electrode has a depressed portion, and wherein the first electrode comprises a protruding portion engaging with the top surface of the second electrode.
Kim teaches, Fig. 1, [0008], wherein a top surface of the second electrode (50) has a depressed portion (as opening), and wherein the first electrode (70) comprises a protruding portion engaging with the top surface of the second electrode (50).
As taught by Kim, one of ordinary skill in the art would utilize & modify the above teaching to obtain a depressed portion in the top surface of the second electrode as claimed, because it aids in increasing the level of integration of the formed device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination Liao due to above reason.
Double Patenting
8. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-12 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of copending Application No. 18/834,280 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because they both require similar claimed limitations and structure such as first-third transistors, first/second capacitors, connection between source/drain to 2nd electrode, and overlapping between first electrode and 2nd/3rd electrodes, first/second transistors, connection electrode & depressed portion of second electrode, etc.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Current application 18/837,718
1. A memory device comprising;
a first transistor;
a second transistor;
a third transistor;
a first capacitor; and
a second capacitor,
wherein the first capacitor comprises a first electrode and a second electrode,
wherein the second capacitor comprises the first electrode and a third electrode,
wherein one of a source and a drain of the first transistor is electrically connected to the second electrode,
wherein one of a source and a drain of the second transistor is electrically connected to the third electrode,
wherein a gate of the third transistor is electrically connected to the second electrode, wherein the first electrode comprises a portion overlapping with each of the second electrode, the third electrode, the first transistor, and the second transistor, and
wherein the first electrode is supplied with a fixed potential or a ground potential.
12. A memory device comprising:
a first transistor;
a second transistor;
a first capacitor; and
a second capacitor,
wherein the first capacitor comprises a first electrode and a second electrode,
wherein the second capacitor comprises the first electrode and a third electrode,
wherein one of a source and a drain of the first transistor is electrically connected to the second electrode,
wherein one of a source and a drain of the second transistor is electrically connected to the third electrode,
wherein a first conductive layer comprising a region configured to function as the first electrode comprises a portion over and overlapping with the second electrode, the third electrode, the first transistor, and the second transistor, and
wherein the first conductive layer comprises a portion provided below the second electrode and the third electrode.
Copending application 18/834,280
1. A storage device comprising:
a first transistor;
a second transistor;
a first capacitor; and
a second capacitor,
wherein the first capacitor comprises a first electrode and a second electrode,
wherein the second capacitor comprises the first electrode and a third electrode,
wherein one of a source and a drain of the first transistor is electrically connected to the second electrode,
wherein one of a source and a drain of the second transistor is electrically connected to the third electrode, and
wherein the first electrode comprises a portion overlapping with each of the second electrode, the third electrode, the first transistor, and the second transistor and is supplied with a fixed potential or a ground potential.
5. The storage device according to claim 3, further comprising:
a third transistor; and
a third capacitor,
wherein the third transistor and the third capacitor are below the first transistor,
wherein the third capacitor comprises a fourth electrode and a fifth electrode,
wherein the fourth electrode is supplied with a ground potential or a fixed potential, and
wherein one of a source and a drain of the third transistor is electrically connected to the fifth electrode, and the other of the source and the drain of the third transistor is electrically connected to the connection electrode.
Allowable Subject Matter
9. Claims 7-8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, and Double Patenting set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kanaya (US 2008/0217669, Fig. 1) discloses semiconductor memory device including stack of memory capacitors and transistors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/1/26
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