Prosecution Insights
Last updated: October 01, 2026
Application No. 18/839,728

CORE SUBSTRATE FOR WIRING BOARDS AND METHOD FOR PRODUCING SAME, AND WIRING BOARD AND METHOD FOR PRODUCING SAME

Non-Final OA §102§103
Filed
Oct 10, 2024
Priority
Feb 22, 2022 — nonprovisional of PCTJP2022007179
Examiner
NORRIS, JEREMY C
Art Unit
Tech Center
Assignee
RESONAC Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
871 granted / 1004 resolved
+26.8% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
12 currently pending
Career history
1017
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
42.8%
+2.8% vs TC avg
§102
50.8%
+10.8% vs TC avg
§112
4.9%
-35.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1004 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 8 and 10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2005/0073047 A1 (Miura). Miura discloses, referring primarily to figures 1-3, a core substrate (2) for wiring boards comprising: a fiber base material; and an insulating resin layer impregnated into the fiber base material ([0031]-[0032]), wherein the core substrate for wiring boards has a first main surface and a second main surface on a rear side of the first main surface; and at least one of the first main surface or the second main surface is a flat surface having an arithmetic mean roughness Ra of 10 nm or less ([0040], [0098]) [claim 8]. Additionally, Miura discloses a wiring board comprising: the core substrate for wiring boards according to claim 8 (as described above); and a wiring layer (3, 4) provided on the flat surface ([0073]-[0074]) [claim 10]. Claim(s) 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2014/0118964 A1 (Nakamura). Nakamura a core substrate for wiring boards comprising: a fiber base material; and an insulating resin layer impregnated into the fiber base material ([0107]), wherein the core substrate for wiring boards has a first main surface and a second main surface on a rear side of the first main surface; and at least one of the first main surface or the second main surface is a flat surface having an arithmetic mean roughness Ra of 10 nm or less ([0160]) [claim 8], wherein the insulating resin layer has a modified region including a void, which is provided in a surface layer portion on a flat surface side of the core substrate ([0116]-[0121]) [claim 9]. Additionally, Nakamura discloses a wiring board comprising: the core substrate for wiring boards according to claim 8 (as described above); and a wiring layer provided on the flat surface ([0135]-[0159]) [claim 10]. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1 and 3-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2008/0047742 A1 (Samejima) in view of US 2005/0146403 A1 (Okubora). Samejima discloses, referring primarily to figures 2A-5, a method for producing a core substrate for wiring boards, the method comprising: hot pressing ([0042]) an intermediate base material (50a, 50b, 2a, 2b, 2c) comprising a fiber base material (3a, be) and a thermosetting resin composition (4a, 4b, 2a, 2b, 2c; [0036]) impregnated into the fiber base material, thereby forming a core substrate having a core portion having a first main surface and a second main surface on a rear side of the first main surface, the core portion comprising the fiber base material and an insulating resin layer that is the cured or semi-cured thermosetting resin composition ([0039]-[0042]). Samejima does not specifically disclose planarizing at least one surface of the first main surface or the second main surface, thereby forming a flat surface [claim 1]. However, it is well known in the art to flatten the surface of a fiber impregnated resin substrate as evidenced by Okubora ([0018]-[0023]). Therefore, it would have been obvious, to one having ordinary skill in the art, to incorporate the claimed features into the invention of Samejima. The motivation for doing so would have been to a substrate suitable for high precision component formation (Okubora [0023]). Additionally, the modified invention of Samejima teaches wherein at least one surface of the first main surface or the second main surface is planarized by a polishing method, a fly cutting method, or a combination thereof (Okubora [0023]) [claim 3], wherein the fiber base material is located beneath the flat surface (Samejima, figure 2E, [0042]) [claim 4], further comprising forming a modified region including a void (8a, Samejima figure 3D) in the insulating resin layer [claim 6] and forming a wiring layer on the flat surface (51a, 51b) [claim 7]. Regarding claim 5, though the modified invention of Samejima does not specifically teach that in the core substrate before the flat surface is formed, the fiber base material is located in a region at a depth of 1 µm or more from a surface to be planarized of the first main surface or second main surface [claim 5], such a modification would involve a mere rearrangement of the working parts of the modified invention of Samejima, which has been held to be within the skill of the ordinary artisan (MPEP 2144). Therefore, it would have been obvious, to one having ordinary skill in the art, to incorporate the claimed features into the modified invention of Samejima. The motivation for doing so would have been to ensure sufficient resin was available for polishing without exposing the fiber material. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Samejima in view of Okubora as applied to claim 1 above, and further in view of Miura. The modified invention of Samejima teaches the claimed invention as described above except modified Samejima does not specifically teach the flat surface having an arithmetic mean roughness Ra of 10 nm or less is formed by planarizing at least one surface of the first main surface or the second main surface. However, planarizing a fiber infused resin in the claimed manner is well known in the art as evidenced by Miura ([0040], [0098]). Therefore, it would have been obvious, to one having ordinary skill in the art, to incorporate the claimed features into the modified invention of Samejima, The motivation for doing so would have been to improve adhesion between insulating and conductive layers (Miura [0040]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMY C NORRIS whose telephone number is (571)272-1932. The examiner can normally be reached 7:15-15:15 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JEREMY C. NORRIS Examiner Art Unit 2847 /JEREMY C NORRIS/Primary Examiner, Art Unit 2847
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Prosecution Timeline

Oct 10, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12738391
ARTICLE WITH ELECTRICALLY-CONDUCTIVE PATTERN
3y 1m to grant Granted Sep 15, 2026
Patent 12733101
PRINTED WIRING BOARD
2y 7m to grant Granted Sep 08, 2026
Patent 12720670
SEMICONDUCTOR SUBSTRATE, METHOD FOR DESIGNING SEMICONDUCTOR SUBSTRATE, AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE
2y 10m to grant Granted Aug 25, 2026
Patent 12720677
WIRING CIRCUIT BOARD AND WIRING CIRCUIT BOARD ASSEMBLY SHEET
2y 9m to grant Granted Aug 25, 2026
Patent 12713529
COMPONENT MOUNTING BOARD
2y 8m to grant Granted Aug 18, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
91%
With Interview (+4.4%)
2y 4m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1004 resolved cases by this examiner. Grant probability derived from career allowance rate.

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