DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 12-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cha et al. (U.S. Patent No. 8,595,657).
Regarding to claim 1, Cha teaches a pattern inspection method for inspecting a pattern, which is either a resist pattern or a conductor pattern formed on a target substrate that is either a printed circuit board or a semiconductor package substrate for mounting of semiconductor elements, the method comprising:
a coordinate measuring step for measuring coordinates of a contour of the pattern (Fig. 1, step S10, column 5, lines 51-63); and
an inspection step for inspecting the pattern based on the measured coordinates (Fig. 1, step S40, column 7, lines 19-26).
Regarding to claim 2, Cha teaches in the inspection step, as the inspection of the pattern, a roughness of the pattern is calculated based on the measured coordinates (column 7, lines 21-24, roughness related to height, critical dimension, sidewall profiles, angle).
Regarding to claim 3, Cha teaches in the inspection step, as the inspection of the pattern, a variation in a contour of the pattern is calculated based on the measured coordinates (column 7, lines 25-26).
Regarding to claim 4, Cha teaches in the inspection step, as the inspection of the pattern, a line width of the pattern and a variation in the line width are calculated based on the measured coordinates (column 7, lines 26-27, CD (critical dimensions) is line width).
Regarding to claim 5, Cha teaches in the inspection step, as the inspection of the pattern, the measured coordinates are compared with pattern data for forming the pattern (column 7, lines 27-31, lines 35-36).
Regarding to claim 12, Cha teaches in the coordinate measuring step, the coordinates of the contour of the pattern are measured based on reflected light from the target substrate (column 5, lines 63-66, microscope measures dimensions based on reflected light from the target substrate).
Regarding to claim 13, Cha teaches in the coordinate measuring step, the coordinates of the contour of the pattern are measured based on fluorescent light from the target substrate (column 5, lines 63-66, CD SEM is measurement tool based on fluorescent light from target substrate).
Regarding to claim 14, Cha teaches in the coordinate measuring step, the coordinates of the contour of the pattern are measured based on an electron beam from the target substrate (column 5, lines 63-66, CD SEM is critical dimension scanning electron microscope).
Regarding to claim 15, Cha teaches a resist pattern manufacturing method, comprising:
a resist pattern forming step for forming a resist pattern on a target substrate, which is either a printed circuit board or a semiconductor package substrate for mounting of semiconductor elements (column 5, line 52);
a coordinate measuring step for measuring coordinates of a contour of the resist pattern after the resist pattern forming step (Fig. 1, step S10, column 5, lines 51-63); and
an inspection step for inspecting the resist pattern based on the coordinates (Fig. 1, step S40, column 7, lines 19-26).
Regarding to claim 16, Cha teaches in the coordinate measuring step, the coordinates of the contour of the resist pattern are measured based on reflected light from the target substrate, fluorescent light from the target substrate, or an electron beam from the target substrate (column 5, lines 63-66).
Regarding to claim 17, Cha teaches a target substrate selection method for selecting a target substrate, which is either a printed circuit board or a semiconductor package substrate for mounting of semiconductor elements, the method comprising:
a coordinate measuring step for measuring coordinates of a contour of a pattern, which is either a resist pattern or a conductor pattern formed on the target substrate (Fig. 1, step S10, column 5, lines 51-63);
an inspection step for inspecting the pattern based on the measured coordinates (Fig. 1, step S30, column 6, lines 40-43); and
an evaluation step for evaluating the pattern based on an inspection result in the inspection step (Fig. 1, step S40, column 7, lines 19-26).
Regarding to claim 18, Cha teaches in the inspection step, as the inspection of the pattern, a roughness of the pattern is calculated based on the measured coordinates, and in the evaluation step, the pattern is evaluated based on the roughness of the pattern (column 7, lines 21-24, roughness related to height, critical dimension, sidewall profiles, angle).
Regarding to claim 19, Cha teaches in the inspection step, as the inspection of the pattern, a variation in the contour is calculated based on the measured coordinates, and in the evaluation step, the pattern is evaluated based on the variation in the contour (column 5, lines 60-63).
Regarding to claim 20, Cha teaches in the inspection step, as the inspection of the pattern, a line width of the pattern and a variation in the line width are calculated based on the measured coordinates, and in the evaluation step, the pattern is evaluated based on the calculated variation in the line width (column 7, lines 26-27, CD (critical dimensions) is line width)).
Regarding to claim 21, Cha teaches in the inspection step, as the inspection of the pattern, the measured coordinates are compared with pattern data for forming the pattern, and in the evaluation step, the pattern is evaluated based on a result of comparison between the measured coordinates and the pattern data (column 6, lines 61-64).
Regarding to claim 22, Cha teaches in the coordinate measuring step, the coordinates of the contour of the pattern are measured based on reflected light from the target substrate, fluorescent light from the target substrate, or an electron beam from the target substrate (column 6, lines 1-7).
Claims 1-2, 4-5, 12, 14, 17-20, and 22-23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ootsuga et al. (U.S. Patent No. 12,512,294).
Regarding to claim 1, Ootsuga teaches a pattern inspection method for inspecting a pattern, which is either a resist pattern or a conductor pattern formed on a target substrate that is either a printed circuit board or a semiconductor package substrate for mounting of semiconductor elements (Fig. 7, element 108; column 8, lines 40-43), the method comprising:
a coordinate measuring step for measuring coordinates of a contour of the pattern (column 8, lines 15-17); and
an inspection step for inspecting the pattern based on the measured coordinates (column 8, lines 18-19).
Regarding to claim 2, Ootsuga teaches in the inspection step, as the inspection of the pattern, a roughness of the pattern is calculated based on the measured coordinates (column 8, lines 47-49).
Regarding to claim 4, Ootsuga teaches in the inspection step, as the inspection of the pattern, a line width of the pattern and a variation in the line width are calculated based on the measured coordinates (column 8, lines 42-44).
Regarding to claim 5, Ootsuga teaches in the inspection step, as the inspection of the pattern, the measured coordinates are compared with pattern data for forming the pattern (column 8, lines 6-10).
Regarding to claim 12, Ootsuga teaches in the coordinate measuring step, the coordinates of the contour of the pattern are measured based on reflected light from the target substrate (Fig. 7, column 7, lines 19-21).
Regarding to claim 14, Ootsuga teaches in the coordinate measuring step, the coordinates of the contour of the pattern are measured based on an electron beam from the target substrate (column 7, lines 13-14).
Regarding to claim 17, Ootsuga teaches a target substrate selection method for selecting a target substrate, which is either a printed circuit board or a semiconductor package substrate for mounting of semiconductor elements (Fig. 7, element 108; column 8, lines 40-43), the method comprising:
a coordinate measuring step for measuring coordinates of a contour of a pattern, which is either a resist pattern or a conductor pattern formed on the target substrate (column 8, lines 15-17);
an inspection step for inspecting the pattern based on the measured coordinates (column 8, lines 18-19); and
an evaluation step for evaluating the pattern based on an inspection result in the inspection step (column 8, lines 23-26).
Regarding to claim 18, Ootsug teaches in the inspection step, as the inspection of the pattern, a roughness of the pattern is calculated based on the measured coordinates, and in the evaluation step, the pattern is evaluated based on the roughness of the pattern (column 8, lines 47-49).
Regarding to claim 19, Ootsug teaches in the inspection step, as the inspection of the pattern, a variation in the contour is calculated based on the measured coordinates, and in the evaluation step, the pattern is evaluated based on the variation in the contour (column 8, lines 15-17).
Regarding to claim 20, Ootsug teaches in the inspection step, as the inspection of the pattern, a line width of the pattern and a variation in the line width are calculated based on the measured coordinates, and in the evaluation step, the pattern is evaluated based on the calculated variation in the line width (column 8, lines 40-42).
Regarding to claim 22, Ootsug teaches in the coordinate measuring step, the coordinates of the contour of the pattern are measured based on reflected light from the target substrate, fluorescent light from the target substrate, or an electron beam from the target substrate (Fig. 7).
Regarding to claim 23, Ootsug teaches a conductor pattern forming step for forming the conductor pattern by performing etching processing or plating processing on the target substrate on which the resist pattern is formed, the resist pattern satisfying criteria for the evaluation of the resist pattern in the target substrate selection method according to claim 17 (column 1, lines 25-28).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (U.S. Patent No. 8,595,657), as applied to claim 1 above, in view of Ishiguro et al. (U.S. Patent No. 10,667,391).
Regarding to claim 6, Cha does not disclose the target substrate contains an inorganic component containing at least one of silica filler and glass cloth and an organic component containing at least one of maleimide resin, bismaleimide-triazine resin, epoxy resin, phenolic resin, cyanate resin, isocyanate resin, benzoxazine resin, oxetane resm, amino resin, unsaturated polyester resin, allyl resin, dicyclopentadiene resin, triazine resin, melamine resin, and polyethylene terephthalate resin. Ishiguro discloses a target substrate contains an inorganic component containing at least one of silica filler and glass cloth and an organic component containing at least one of maleimide resin, bismaleimide-triazine resin, epoxy resin, phenolic resin, cyanate resin, isocyanate resin, benzoxazine resin, oxetane resm, amino resin, unsaturated polyester resin, allyl resin, dicyclopentadiene resin, triazine resin, melamine resin, and polyethylene terephthalate resin (column 12, lines 14-18). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cha in view of Ishiguro to contain in the target substrate an inorganic component containing at least one of silica filler and glass cloth and an organic component containing at least one of maleimide resin, bismaleimide-triazine resin, epoxy resin, phenolic resin, cyanate resin, isocyanate resin, benzoxazine resin, oxetane resin, amino resin, unsaturated polyester resin, allyl resin, dicyclopentadiene resin, triazine resin, melamine resin, and polyethylene terephthalate resin in order to make the patterning useful for a particular application.
Regarding to claim 7, Cha does not disclose the target substrate includes at least one of a core layer and a build-up layer. Ishiguro discloses the target substrate includes at least one of a core layer and a build-up layer (Fig. 1A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cha in view of Ishiguro to include in the target substrate at least one of a core layer and a build-up layer in order to make the patterning useful for a particular application.
Claims 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (U.S. Patent No. 8,595,657), as applied to claim 1 above.
Regarding to claim 8, Cha discloses a thickness in the figures but is silent as to dimension in the text. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of the target substrate to be 50 μm or more and 3000 μm or less in order to obtain sufficient strength with less thermal stress, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 11, Cha discloses the pattern is the resist pattern (column 5, lines 51-52). Cha is silent as to dimension, however, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of the resist pattern to be 3 μm or more and 200 μm or less in order to obtain sufficient blocking capability with less removing time after patterning, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Allowable Subject Matter
Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 9, the prior art fails to anticipate or render obvious the claimed limitations including “the resist pattern contains a binder polymer having a carboxyl group, a radical polymerizable compound having an ethylenically unsaturated bond, and a photoradical polymerization initiator” in combination with the limitations recited in claim 1 and the rest of limitations recited in claim 9.
Regarding to claim 10, the prior art fails to anticipate or render obvious the claimed limitations including “a resin film is provided on the resist pattern, and in the coordinate measuring step, the coordinates of the contour of the pattern are measured through the resin film” in combination with the limitations recited in claim 1 and the rest of limitations recited in claim 10.
Pertinent Art
For the benefits of the Applicant, US-9230818-B2, US-6784446-B1, US-6850320-B2, US-7127098-B2, US-7681159-B2US-12019032-B2, US-11043417-B2, US-20110133066-A1, US-7689029-B2, and US-9921487-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose the combination of limitations including “a coordinate measuring step for measuring coordinates of a contour of the pattern and an inspection step for inspecting the pattern based on the measured coordinates.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
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/VU A VU/Primary Examiner, Art Unit 2897
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